| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_vm.c | 130 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
151 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
153 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
155 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_num_entries()
177 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_num_ats_entries()
193 if (level <= adev->vm_manager.root_level) in amdgpu_vm_entries_mask()
397 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
750 unsigned level = adev->vm_manager.root_level; in amdgpu_vm_clear_bo()
1039 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
1078 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager in amdgpu_vm_flush()
[all...] |
| H A D | amdgpu_ids.c | 203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
219 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
230 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
231 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
297 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
347 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
375 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
415 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
477 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
504 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager in amdgpu_vmid_free_reserved()
[all...] |
| H A D | amdgpu_vm.h | 51 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
364 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
365 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
366 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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| H A D | gfxhub_v2_1.c | 168 + adev->vm_manager.vram_base_offset; in gfxhub_v2_1_init_system_aperture_regs()
301 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
318 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
331 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
334 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
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| H A D | gfxhub_v2_0.c | 169 + adev->vm_manager.vram_base_offset; in gfxhub_v2_0_init_system_aperture_regs()
295 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
312 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
325 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
328 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
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| H A D | gfxhub_v1_0.c | 102 adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_system_aperture_regs()
215 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
216 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
257 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
260 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
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| H A D | gmc_v6_0.c | 445 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
504 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
528 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
549 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
590 adev->vm_manager.saved_table_addr[i] = RREG32(reg); in gmc_v6_0_gart_disable()
878 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
886 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
888 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
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| H A D | mmhub_v2_0.c | 213 adev->vm_manager.vram_base_offset; in mmhub_v2_0_init_system_aperture_regs()
350 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
368 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
381 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
384 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
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| H A D | gmc_v7_0.c | 574 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
646 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
675 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
693 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1053 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1061 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1063 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_vm.c | 149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid)); in amdgpu_vm_set_pasid()
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, in amdgpu_vm_set_pasid()
384 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
385 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
390 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
391 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
571 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
605 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
1113 vram_base = bo_adev->vm_manager.vram_base_offset; in amdgpu_vm_bo_update()
1196 spin_lock_irqsave(&adev->vm_manager in amdgpu_vm_update_prt_state()
[all...] |
| H A D | amdgpu_ids.c | 206 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
223 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
234 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
235 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
281 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_reserved()
297 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
342 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
368 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
402 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
465 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager in amdgpu_vmid_alloc_reserved()
[all...] |
| H A D | amdgpu_vm_pt.c | 57 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift()
79 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_entries()
80 if (level == adev->vm_manager.root_level) in amdgpu_vm_pt_num_entries()
82 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_pt_num_entries()
104 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_ats_entries()
120 if (level <= adev->vm_manager.root_level) in amdgpu_vm_pt_entries_mask()
179 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
378 unsigned int level = adev->vm_manager.root_level; in amdgpu_vm_pt_clear()
746 enum amdgpu_vm_level root = adev->vm_manager.root_level; in amdgpu_vm_pt_is_root_clean()
777 level += params->adev->vm_manager in amdgpu_vm_pde_update()
[all...] |
| H A D | mmhub_v3_0_1.c | 192 adev->vm_manager.vram_base_offset; in mmhub_v3_0_1_init_system_aperture_regs()
317 adev->vm_manager.num_level); in mmhub_v3_0_1_setup_vmid_config()
335 adev->vm_manager.block_size - 9); in mmhub_v3_0_1_setup_vmid_config()
348 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
351 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
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| H A D | mmhub_v3_0_2.c | 185 adev->vm_manager.vram_base_offset; in mmhub_v3_0_2_init_system_aperture_regs()
322 adev->vm_manager.num_level); in mmhub_v3_0_2_setup_vmid_config()
340 adev->vm_manager.block_size - 9); in mmhub_v3_0_2_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
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| H A D | gfxhub_v3_0_3.c | 173 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_3_init_system_aperture_regs()
306 adev->vm_manager.num_level); in gfxhub_v3_0_3_setup_vmid_config()
323 adev->vm_manager.block_size - 9); in gfxhub_v3_0_3_setup_vmid_config()
336 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
339 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
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| H A D | gfxhub_v3_0.c | 168 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_init_system_aperture_regs()
301 adev->vm_manager.num_level); in gfxhub_v3_0_setup_vmid_config()
318 adev->vm_manager.block_size - 9); in gfxhub_v3_0_setup_vmid_config()
331 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
334 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
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| H A D | gmc_v6_0.c | 438 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
495 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
519 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
540 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
580 adev->vm_manager.saved_table_addr[i] = RREG32(reg); in gmc_v6_0_gart_disable()
867 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
875 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
877 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
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| H A D | mmhub_v3_0.c | 193 adev->vm_manager.vram_base_offset; in mmhub_v3_0_init_system_aperture_regs()
330 adev->vm_manager.num_level); in mmhub_v3_0_setup_vmid_config()
348 adev->vm_manager.block_size - 9); in mmhub_v3_0_setup_vmid_config()
361 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
364 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
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| H A D | gfxhub_v1_0.c | 257 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
258 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
303 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
306 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
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| H A D | amdgpu_vm.h | 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
389 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
390 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
391 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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| H A D | gfxhub_v2_0.c | 293 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
310 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
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| H A D | mmhub_v2_3.c | 291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
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| H A D | mmhub_v2_0.c | 373 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
391 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | radeon_vm.c | 62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
188 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
195 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
196 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
215 return rdev->vm_manager in radeon_vm_grab_id()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | radeon_vm.c | 62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
189 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
196 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
197 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
216 return rdev->vm_manager in radeon_vm_grab_id()
[all...] |