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Help
Searched
refs:quad_enable
(Results
1 - 15
of
15
) sorted by relevance
/kernel/linux/linux-5.10/drivers/mtd/spi-nor/
H
A
D
gigadevice.c
16
* indicate the
quad_enable
method for this case, we need
in gd25q256_default_init()
19
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in gd25q256_default_init()
H
A
D
sfdp.c
561
params->
quad_enable
= NULL;
in spi_nor_parse_bfpt()
575
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_parse_bfpt()
580
params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in spi_nor_parse_bfpt()
585
params->
quad_enable
= spi_nor_sr2_bit7_quad_enable;
in spi_nor_parse_bfpt()
597
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_parse_bfpt()
H
A
D
macronix.c
94
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in macronix_default_init()
H
A
D
issi.c
71
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in issi_default_init()
H
A
D
micron-st.c
141
nor->params->
quad_enable
= NULL;
in micron_st_default_init()
H
A
D
core.h
201
* @
quad_enable
: enables SPI NOR quad mode.
222
int (*
quad_enable
)(struct spi_nor *nor);
member
H
A
D
core.c
805
nor->params->
quad_enable
) {
in spi_nor_write_16bit_sr_and_check()
813
* consequence of the nor->params->
quad_enable
() call.
in spi_nor_write_16bit_sr_and_check()
2748
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_info_init_params()
2930
if (!nor->params->
quad_enable
)
in spi_nor_quad_enable()
2937
return nor->params->
quad_enable
(nor);
in spi_nor_quad_enable()
/kernel/linux/linux-6.6/drivers/mtd/spi-nor/
H
A
D
gigadevice.c
27
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in gd25q256_post_bfpt()
H
A
D
issi.c
96
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in issi_nor_default_init()
H
A
D
macronix.c
110
nor->params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in macronix_nor_default_init()
H
A
D
sfdp.c
572
params->
quad_enable
= NULL;
in spi_nor_parse_bfpt()
586
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_parse_bfpt()
591
params->
quad_enable
= spi_nor_sr1_bit6_quad_enable;
in spi_nor_parse_bfpt()
596
params->
quad_enable
= spi_nor_sr2_bit7_quad_enable;
in spi_nor_parse_bfpt()
608
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_parse_bfpt()
H
A
D
micron-st.c
151
nor->params->
quad_enable
= NULL;
in mt35xu512aba_post_sfdp_fixup()
429
nor->params->
quad_enable
= NULL;
in micron_st_nor_default_init()
H
A
D
core.h
368
* @
quad_enable
: enables SPI NOR quad mode.
403
int (*
quad_enable
)(struct spi_nor *nor);
member
H
A
D
core.c
875
nor->params->
quad_enable
) {
in spi_nor_write_16bit_sr_and_check()
883
* consequence of the nor->params->
quad_enable
() call.
in spi_nor_write_16bit_sr_and_check()
2996
params->
quad_enable
= spi_nor_sr2_bit1_quad_enable;
in spi_nor_init_default_params()
3141
if (!nor->params->
quad_enable
)
in spi_nor_quad_enable()
3148
return nor->params->
quad_enable
(nor);
in spi_nor_quad_enable()
H
A
D
spansion.c
597
nor->params->
quad_enable
= cypress_nor_quad_enable_volatile;
in s25hx_t_post_bfpt_fixup()
Completed in 18 milliseconds