18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2005, Intec Automation Inc. 48c2ecf20Sopenharmony_ci * Copyright (C) 2014, Freescale Semiconductor, Inc. 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#include <linux/mtd/spi-nor.h> 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include "core.h" 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_cistatic void gd25q256_default_init(struct spi_nor *nor) 128c2ecf20Sopenharmony_ci{ 138c2ecf20Sopenharmony_ci /* 148c2ecf20Sopenharmony_ci * Some manufacturer like GigaDevice may use different 158c2ecf20Sopenharmony_ci * bit to set QE on different memories, so the MFR can't 168c2ecf20Sopenharmony_ci * indicate the quad_enable method for this case, we need 178c2ecf20Sopenharmony_ci * to set it in the default_init fixup hook. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; 208c2ecf20Sopenharmony_ci} 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_cistatic struct spi_nor_fixups gd25q256_fixups = { 238c2ecf20Sopenharmony_ci .default_init = gd25q256_default_init, 248c2ecf20Sopenharmony_ci}; 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_cistatic const struct flash_info gigadevice_parts[] = { 278c2ecf20Sopenharmony_ci { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 288c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 298c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 308c2ecf20Sopenharmony_ci { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 318c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 328c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 338c2ecf20Sopenharmony_ci { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 348c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 358c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 368c2ecf20Sopenharmony_ci { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 378c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 388c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 398c2ecf20Sopenharmony_ci { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, 408c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 418c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 428c2ecf20Sopenharmony_ci { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256, 438c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 448c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 458c2ecf20Sopenharmony_ci { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, 468c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 478c2ecf20Sopenharmony_ci SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 488c2ecf20Sopenharmony_ci { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, 498c2ecf20Sopenharmony_ci SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 508c2ecf20Sopenharmony_ci SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 518c2ecf20Sopenharmony_ci SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) 528c2ecf20Sopenharmony_ci .fixups = &gd25q256_fixups }, 538c2ecf20Sopenharmony_ci}; 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ciconst struct spi_nor_manufacturer spi_nor_gigadevice = { 568c2ecf20Sopenharmony_ci .name = "gigadevice", 578c2ecf20Sopenharmony_ci .parts = gigadevice_parts, 588c2ecf20Sopenharmony_ci .nparts = ARRAY_SIZE(gigadevice_parts), 598c2ecf20Sopenharmony_ci}; 60