| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 32 * MediaTek PLLs are configured through their pcw value. The pcw value describes
63 u32 pcw, int postdiv) in __mtk_pll_recalc_rate()
76 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
115 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
128 /* postdiv and pcw need to set at the same time if on same register */ in mtk_pll_set_rate_regs()
134 /* set pcw */ in mtk_pll_set_rate_regs()
137 val |= pcw << pll->data->pcw_shift; in mtk_pll_set_rate_regs()
153 * @pcw: The pcw valu
62 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) __mtk_pll_recalc_rate() argument
159 mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin) mtk_pll_calc_values() argument
200 u32 pcw = 0; mtk_pll_set_rate() local
214 u32 pcw; mtk_pll_recalc_rate() local
229 u32 pcw = 0; mtk_pll_round_rate() local
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate()
54 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
106 /* postdiv and pcw need to set at the same time if on same register */ in mtk_pll_set_rate_regs()
112 /* set pcw */ in mtk_pll_set_rate_regs()
115 val |= pcw << pll->data->pcw_shift; in mtk_pll_set_rate_regs()
131 * @pcw: The pcw value (output)
137 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
171 *pcw in mtk_pll_calc_values()
40 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) __mtk_pll_recalc_rate() argument
178 u32 pcw = 0; mtk_pll_set_rate() local
191 u32 pcw; mtk_pll_recalc_rate() local
206 u32 pcw = 0; mtk_pll_round_rate() local
[all...] |
| H A D | clk-pllfh.c | 32 u32 pcw = 0; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
|
| H A D | clk-pll.h | 54 * MediaTek PLLs are configured through their pcw value. The pcw value describes
94 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/ |
| H A D | mtk_mt8183_mipi_tx.c | 50 u64 pcw; in mtk_mipi_tx_pll_enable() local
79 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_enable()
80 writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0); in mtk_mipi_tx_pll_enable()
|
| H A D | mtk_mt8173_mipi_tx.c | 120 u64 pcw; in mtk_mipi_tx_pll_prepare() local
179 * PCW bit 24~30 = integer part of pcw in mtk_mipi_tx_pll_prepare()
180 * PCW bit 0~23 = fractional part of pcw in mtk_mipi_tx_pll_prepare()
181 * pcw = data_Rate*4*txdiv/(Ref_clk*2); in mtk_mipi_tx_pll_prepare()
185 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, in mtk_mipi_tx_pll_prepare()
187 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); in mtk_mipi_tx_pll_prepare()
|
| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi-mt8183.c | 52 u64 pcw; in mtk_mipi_tx_pll_enable() local
81 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_enable()
82 writel(pcw, base + MIPITX_PLL_CON0); in mtk_mipi_tx_pll_enable()
|
| H A D | phy-mtk-hdmi-mt8195.c | 213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc() local
269 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; in mtk_hdmi_pll_calc()
273 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, in mtk_hdmi_pll_calc()
276 if (pcw > GENMASK_ULL(32, 0)) in mtk_hdmi_pll_calc()
279 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw); in mtk_hdmi_pll_calc()
280 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw); in mtk_hdmi_pll_calc()
|
| H A D | phy-mtk-mipi-dsi-mt8173.c | 127 u64 pcw; in mtk_mipi_tx_pll_prepare() local
190 * PCW bit 24~30 = integer part of pcw in mtk_mipi_tx_pll_prepare()
191 * PCW bit 0~23 = fractional part of pcw in mtk_mipi_tx_pll_prepare()
192 * pcw = data_Rate*4*txdiv/(Ref_clk*2); in mtk_mipi_tx_pll_prepare()
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_prepare()
197 writel(pcw, base + MIPITX_DSI_PLL_CON2); in mtk_mipi_tx_pll_prepare()
|