Lines Matching refs:pcw
32 * MediaTek PLLs are configured through their pcw value. The pcw value describes
63 u32 pcw, int postdiv)
76 vco = (u64)fin * pcw;
115 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
128 /* postdiv and pcw need to set at the same time if on same register */
134 /* set pcw */
137 val |= pcw << pll->data->pcw_shift;
153 * @pcw: The pcw value (output)
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
193 *pcw = (u32)_pcw;
200 u32 pcw = 0;
203 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
204 mtk_pll_set_rate_regs(pll, pcw, postdiv);
214 u32 pcw;
219 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
220 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
222 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
229 u32 pcw = 0;
232 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
234 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);