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/kernel/linux/linux-5.10/drivers/clk/ingenic/
H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
344 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
350 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
356 .parents
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H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
153 .parents = { JZ4770_CLK_PLL0, },
161 .parents = { JZ4770_CLK_PLL0, },
169 .parents = { JZ4770_CLK_PLL0, },
178 .parents = { JZ4770_CLK_PLL0, },
186 .parents = { JZ4770_CLK_PLL0, },
195 .parents = { JZ4770_CLK_PLL0, },
206 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
213 .parents
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H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
228 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
235 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents
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H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
90 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
99 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
108 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
117 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
126 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
143 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
150 .parents
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H A Dx1000-cgu.c186 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
209 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
234 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
242 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
248 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
254 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
261 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
267 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
274 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
280 .parents
[all...]
H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
105 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
114 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
123 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
132 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
165 .parents
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/kernel/linux/linux-6.6/drivers/clk/ingenic/
H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
366 .parents
[all...]
H A Djz4755-cgu.c53 .parents = { JZ4755_CLK_EXT, },
78 .parents = { JZ4755_CLK_PLL, },
87 .parents = { JZ4755_CLK_EXT, },
96 .parents = { JZ4755_CLK_PLL, },
105 .parents = { JZ4755_CLK_PLL, },
114 .parents = { JZ4755_CLK_PLL, },
123 .parents = { JZ4755_CLK_PLL, },
132 .parents = { JZ4755_CLK_PLL, },
141 .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, },
149 .parents
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H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
157 .parents = { JZ4770_CLK_PLL0, },
165 .parents = { JZ4770_CLK_PLL0, },
173 .parents = { JZ4770_CLK_PLL0, },
182 .parents = { JZ4770_CLK_PLL0, },
190 .parents = { JZ4770_CLK_PLL0, },
199 .parents = { JZ4770_CLK_PLL0, },
210 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
217 .parents
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H A Djz4760-cgu.c94 .parents = { JZ4760_CLK_EXT },
119 .parents = { JZ4760_CLK_EXT },
149 .parents = { JZ4760_CLK_PLL0, },
157 .parents = { JZ4760_CLK_PLL0, },
165 .parents = { JZ4760_CLK_PLL0, },
173 .parents = { JZ4760_CLK_PLL0, },
182 * Disabling MCLK or its parents will render DRAM
186 .parents = { JZ4760_CLK_PLL0, },
194 .parents = { JZ4760_CLK_PLL0, },
205 .parents
[all...]
H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
229 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
247 .parents
[all...]
H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
123 * Disabling MCLK or its parents will render DRAM
127 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
146 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
153 .parents
[all...]
H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
138 * Disabling MCLK or its parents will render DRAM
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents
[all...]
H A Dx1000-cgu.c219 .parents = { X1000_CLK_EXCLK },
242 .parents = { X1000_CLK_EXCLK },
267 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
275 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
281 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
292 .parents = { X1000_CLK_CPUMUX },
304 .parents = { X1000_CLK_CPUMUX },
310 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
317 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
323 .parents
[all...]
/kernel/linux/linux-5.10/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
66 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
67 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
68 pr_err("%s: Failed to get parents (%ld)\n", in st_of_clkgen_mux_setup()
69 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
[all...]
/kernel/linux/linux-6.6/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
76 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
77 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
78 pr_err("%s: Failed to get parents (%ld)\n", in st_of_clkgen_mux_setup()
79 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
[all...]
/kernel/linux/linux-5.10/drivers/clk/zynqmp/
H A Dclkc.c24 /* Flags for parents */
67 * @num_parents: Number of parents of clock
98 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
122 const char * const *parents,
279 * @parents: Name of this clock's parents
280 * @num_parents: Number of parents
286 const char * const *parents, in zynqmp_clk_register_fixed_factor()
307 parents[0], in zynqmp_clk_register_fixed_factor()
315 * zynqmp_pm_clock_get_parents() - Get the first 3 parents o
285 zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes) zynqmp_clk_register_fixed_factor() argument
448 __zynqmp_clock_get_parents(struct clock_parent *parents, struct parents_resp *response, u32 *nparent) __zynqmp_clock_get_parents() argument
484 zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, u32 *num_parents) zynqmp_clock_get_parents() argument
523 struct clock_parent *parents; zynqmp_get_parent_list() local
[all...]
H A Dclk-zynqmp.h37 const char * const *parents,
42 const char * const *parents,
48 const char * const *parents,
53 const char * const *parents,
59 const char * const *parents,
/kernel/linux/linux-6.6/drivers/clk/zynqmp/
H A Dclkc.c25 /* Flags for parents */
68 * @num_parents: Number of parents of clock
99 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
123 const char * const *parents,
304 * @parents: Name of this clock's parents
305 * @num_parents: Number of parents
311 const char * const *parents, in zynqmp_clk_register_fixed_factor()
335 parents[0], in zynqmp_clk_register_fixed_factor()
343 * zynqmp_pm_clock_get_parents() - Get the first 3 parents o
310 zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes) zynqmp_clk_register_fixed_factor() argument
476 __zynqmp_clock_get_parents(struct clock_parent *parents, struct parents_resp *response, u32 *nparent) __zynqmp_clock_get_parents() argument
512 zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, u32 *num_parents) zynqmp_clock_get_parents() argument
551 struct clock_parent *parents; zynqmp_get_parent_list() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h29 u8 parents[4]; member
37 .parents = { [0] = _parent }, \
45 .parents = { [0] = _parent }, \
53 .parents = { [0] = _parent }, \
61 .parents = { [0] = _parent }, \
69 .parents = { __VA_ARGS__ }, \
78 .parents = { __VA_ARGS__ }, \
86 .parents = { __VA_ARGS__ }, \
95 .parents = { __VA_ARGS__ }, \
103 .parents
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H A Dclk-starfive-jh7110-aon.c88 struct clk_parent_data parents[4] = {}; in jh7110_aoncrg_probe() local
92 .parent_data = parents, in jh7110_aoncrg_probe()
101 unsigned int pidx = jh7110_aonclk_data[idx].parents[i]; in jh7110_aoncrg_probe()
104 parents[i].hw = &priv->reg[pidx].hw; in jh7110_aoncrg_probe()
106 parents[i].fw_name = "osc"; in jh7110_aoncrg_probe()
108 parents[i].fw_name = "gmac0_rmii_refin"; in jh7110_aoncrg_probe()
110 parents[i].fw_name = "gmac0_rgmii_rxin"; in jh7110_aoncrg_probe()
112 parents[i].fw_name = "stg_axiahb"; in jh7110_aoncrg_probe()
114 parents[i].fw_name = "apb_bus"; in jh7110_aoncrg_probe()
116 parents[ in jh7110_aoncrg_probe()
[all...]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-bpmp.c23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
208 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
249 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
374 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
415 dev_printk(level, bpmp->dev, " parents: %u\n", info->num_parents); in tegra_bpmp_clk_info_dump()
418 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
450 "clock %u has too many parents (%u, max: %u)\n", in tegra_bpmp_probe_clocks()
509 const char **parents; in tegra_bpmp_clk_register() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-bpmp.c23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
203 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
244 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
351 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
392 dev_printk(level, bpmp->dev, " parents: %u\n", info->num_parents); in tegra_bpmp_clk_info_dump()
395 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
427 "clock %u has too many parents (%u, max: %u)\n", in tegra_bpmp_probe_clocks()
472 const char **parents; in tegra_bpmp_clk_register() local
[all...]

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12345678910>>...13