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Searched refs:crtc_base (Results 1 - 23 of 23) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv770.c808 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rv770_page_flip() argument
822 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
823 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
826 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
829 (u32)crtc_base); in rv770_page_flip()
831 (u32)crtc_base); in rv770_page_flip()
H A Drs600.c118 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rs600_page_flip() argument
132 (u32)crtc_base); in rs600_page_flip()
134 (u32)crtc_base); in rs600_page_flip()
H A Dradeon_asic.h141 u64 crtc_base, bool async);
253 u64 crtc_base, bool async);
467 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
538 u64 crtc_base, bool async);
H A Dr100.c155 * @crtc_base: new address of the crtc (GPU MC address)
162 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in r100_page_flip() argument
165 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; in r100_page_flip()
H A Devergreen.c1413 * @crtc_base: new address of the crtc (GPU MC address)
1418 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, in evergreen_page_flip() argument
1427 upper_32_bits(crtc_base)); in evergreen_page_flip()
1429 (u32)crtc_base); in evergreen_page_flip()
H A Dradeon.h1999 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv770.c800 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rv770_page_flip() argument
819 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
820 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
822 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
823 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
826 (u32)crtc_base); in rv770_page_flip()
828 (u32)crtc_base); in rv770_page_flip()
H A Drs600.c120 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rs600_page_flip() argument
139 (u32)crtc_base); in rs600_page_flip()
141 (u32)crtc_base); in rs600_page_flip()
H A Dradeon_asic.h141 u64 crtc_base, bool async);
252 u64 crtc_base, bool async);
465 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
536 u64 crtc_base, bool async);
H A Dr100.c155 * @crtc_base: new address of the crtc (GPU MC address)
163 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in r100_page_flip() argument
168 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; in r100_page_flip()
H A Devergreen.c1409 * @crtc_base: new address of the crtc (GPU MC address)
1415 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, in evergreen_page_flip() argument
1429 upper_32_bits(crtc_base)); in evergreen_page_flip()
1431 (u32)crtc_base); in evergreen_page_flip()
H A Dradeon.h1989 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Ddce_virtual.c63 int crtc_id, u64 crtc_base, bool async) in dce_virtual_page_flip()
62 dce_virtual_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_virtual_page_flip() argument
H A Damdgpu_mode.h282 int crtc_id, u64 crtc_base, bool async);
H A Ddce_v11_0.c248 * @crtc_base: new address of the crtc (GPU MC address)
254 int crtc_id, u64 crtc_base, bool async) in dce_v11_0_page_flip()
270 upper_32_bits(crtc_base)); in dce_v11_0_page_flip()
273 lower_32_bits(crtc_base)); in dce_v11_0_page_flip()
253 dce_v11_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v11_0_page_flip() argument
H A Ddce_v8_0.c178 * @crtc_base: new address of the crtc (GPU MC address)
184 int crtc_id, u64 crtc_base, bool async) in dce_v8_0_page_flip()
197 upper_32_bits(crtc_base)); in dce_v8_0_page_flip()
200 lower_32_bits(crtc_base)); in dce_v8_0_page_flip()
183 dce_v8_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v8_0_page_flip() argument
H A Ddce_v10_0.c230 * @crtc_base: new address of the crtc (GPU MC address)
236 int crtc_id, u64 crtc_base, bool async) in dce_v10_0_page_flip()
252 upper_32_bits(crtc_base)); in dce_v10_0_page_flip()
255 lower_32_bits(crtc_base)); in dce_v10_0_page_flip()
235 dce_v10_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v10_0_page_flip() argument
H A Ddce_v6_0.c182 * @crtc_base: new address of the crtc (GPU MC address)
191 int crtc_id, u64 crtc_base, bool async) in dce_v6_0_page_flip()
204 upper_32_bits(crtc_base)); in dce_v6_0_page_flip()
206 (u32)crtc_base); in dce_v6_0_page_flip()
190 dce_v6_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v6_0_page_flip() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h278 int crtc_id, u64 crtc_base, bool async);
H A Ddce_v8_0.c178 * @crtc_base: new address of the crtc (GPU MC address)
185 int crtc_id, u64 crtc_base, bool async) in dce_v8_0_page_flip()
198 upper_32_bits(crtc_base)); in dce_v8_0_page_flip()
201 lower_32_bits(crtc_base)); in dce_v8_0_page_flip()
184 dce_v8_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v8_0_page_flip() argument
H A Ddce_v11_0.c250 * @crtc_base: new address of the crtc (GPU MC address)
257 int crtc_id, u64 crtc_base, bool async) in dce_v11_0_page_flip()
273 upper_32_bits(crtc_base)); in dce_v11_0_page_flip()
276 lower_32_bits(crtc_base)); in dce_v11_0_page_flip()
256 dce_v11_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v11_0_page_flip() argument
H A Ddce_v10_0.c226 * @crtc_base: new address of the crtc (GPU MC address)
233 int crtc_id, u64 crtc_base, bool async) in dce_v10_0_page_flip()
249 upper_32_bits(crtc_base)); in dce_v10_0_page_flip()
252 lower_32_bits(crtc_base)); in dce_v10_0_page_flip()
232 dce_v10_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v10_0_page_flip() argument
H A Ddce_v6_0.c184 * @crtc_base: new address of the crtc (GPU MC address)
194 int crtc_id, u64 crtc_base, bool async) in dce_v6_0_page_flip()
207 upper_32_bits(crtc_base)); in dce_v6_0_page_flip()
209 (u32)crtc_base); in dce_v6_0_page_flip()
193 dce_v6_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) dce_v6_0_page_flip() argument

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