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Searched refs:cpt (Results 1 - 25 of 43) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_main.c14 #define DRV_NAME "octeontx-cpt"
17 static void otx_cpt_disable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_disable_mbox_interrupts() argument
20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0)); in otx_cpt_disable_mbox_interrupts()
23 static void otx_cpt_enable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_enable_mbox_interrupts() argument
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0)); in otx_cpt_enable_mbox_interrupts()
30 void *cpt) in otx_cpt_mbx0_intr_handler()
32 otx_cpt_mbox_intr_handler(cpt, 0); in otx_cpt_mbx0_intr_handler()
37 static void otx_cpt_reset(struct otx_cpt_device *cpt) in otx_cpt_reset() argument
39 writeq(1, cpt->reg_base + OTX_CPT_PF_RESET); in otx_cpt_reset()
42 static void otx_cpt_find_max_enabled_cores(struct otx_cpt_device *cpt) in otx_cpt_find_max_enabled_cores() argument
29 otx_cpt_mbx0_intr_handler(int __always_unused irq, void *cpt) otx_cpt_mbx0_intr_handler() argument
51 otx_cpt_check_bist_status(struct otx_cpt_device *cpt) otx_cpt_check_bist_status() argument
59 otx_cpt_check_exe_bist_status(struct otx_cpt_device *cpt) otx_cpt_check_exe_bist_status() argument
67 otx_cpt_device_init(struct otx_cpt_device *cpt) otx_cpt_device_init() argument
112 otx_cpt_register_interrupts(struct otx_cpt_device *cpt) otx_cpt_register_interrupts() argument
142 otx_cpt_unregister_interrupts(struct otx_cpt_device *cpt) otx_cpt_unregister_interrupts() argument
156 struct otx_cpt_device *cpt = pci_get_drvdata(pdev); otx_cpt_sriov_configure() local
193 struct otx_cpt_device *cpt; otx_cpt_probe() local
268 struct otx_cpt_device *cpt = pci_get_drvdata(pdev); otx_cpt_remove() local
[all...]
H A Dotx_cptpf_mbox.c74 static void otx_cpt_send_msg_to_vf(struct otx_cpt_device *cpt, int vf, in otx_cpt_send_msg_to_vf() argument
78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
86 static void otx_cpt_mbox_send_ack(struct otx_cpt_device *cpt, int vf, in otx_cpt_mbox_send_ack() argument
91 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cpt_mbox_send_ack()
95 static void otx_cptpf_mbox_send_nack(struct otx_cpt_device *cpt, int vf, in otx_cptpf_mbox_send_nack() argument
100 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cptpf_mbox_send_nack()
103 static void otx_cpt_clear_mbox_intr(struct otx_cpt_device *cpt, u32 vf) in otx_cpt_clear_mbox_intr() argument
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
112 static void otx_cpt_cfg_qlen_for_vf(struct otx_cpt_device *cpt, in argument
126 otx_cpt_cfg_vq_priority(struct otx_cpt_device *cpt, int vf, u32 pri) otx_cpt_cfg_vq_priority() argument
135 otx_cpt_bind_vq_to_grp(struct otx_cpt_device *cpt, u8 q, u8 grp) otx_cpt_bind_vq_to_grp() argument
178 otx_cpt_handle_mbox_intr(struct otx_cpt_device *cpt, int vf) otx_cpt_handle_mbox_intr() argument
240 otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx) otx_cpt_mbox_intr_handler() argument
[all...]
H A DMakefile2 obj-$(CONFIG_CRYPTO_DEV_OCTEONTX_CPT) += octeontx-cpt.o octeontx-cptvf.o
4 octeontx-cpt-objs := otx_cptpf_main.o otx_cptpf_mbox.o otx_cptpf_ucode.o
H A Dotx_cptpf.h31 void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx);
32 void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt);
H A Dotx_cptpf_ucode.c177 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_set_ucode_base() local
182 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_set_ucode_base()
198 writeq((u64) dma_addr, cpt->reg_base + in cpt_set_ucode_base()
206 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_detach_and_disable_cores() local
212 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_detach_and_disable_cores()
217 reg = readq(cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
224 writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
233 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); in cpt_detach_and_disable_cores()
242 reg = readq(cpt->reg_base + OTX_CPT_PF_EXE_CTL); in cpt_detach_and_disable_cores()
246 writeq(reg, cpt in cpt_detach_and_disable_cores()
254 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; cpt_attach_and_enable_cores() local
1564 otx_cpt_disable_all_cores(struct otx_cpt_device *cpt) otx_cpt_disable_all_cores() argument
[all...]
H A Dotx_cptvf.h22 #define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY)
/kernel/linux/linux-6.6/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_main.c14 #define DRV_NAME "octeontx-cpt"
17 static void otx_cpt_disable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_disable_mbox_interrupts() argument
20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0)); in otx_cpt_disable_mbox_interrupts()
23 static void otx_cpt_enable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_enable_mbox_interrupts() argument
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0)); in otx_cpt_enable_mbox_interrupts()
30 void *cpt) in otx_cpt_mbx0_intr_handler()
32 otx_cpt_mbox_intr_handler(cpt, 0); in otx_cpt_mbx0_intr_handler()
37 static void otx_cpt_reset(struct otx_cpt_device *cpt) in otx_cpt_reset() argument
39 writeq(1, cpt->reg_base + OTX_CPT_PF_RESET); in otx_cpt_reset()
42 static void otx_cpt_find_max_enabled_cores(struct otx_cpt_device *cpt) in otx_cpt_find_max_enabled_cores() argument
29 otx_cpt_mbx0_intr_handler(int __always_unused irq, void *cpt) otx_cpt_mbx0_intr_handler() argument
51 otx_cpt_check_bist_status(struct otx_cpt_device *cpt) otx_cpt_check_bist_status() argument
59 otx_cpt_check_exe_bist_status(struct otx_cpt_device *cpt) otx_cpt_check_exe_bist_status() argument
67 otx_cpt_device_init(struct otx_cpt_device *cpt) otx_cpt_device_init() argument
112 otx_cpt_register_interrupts(struct otx_cpt_device *cpt) otx_cpt_register_interrupts() argument
142 otx_cpt_unregister_interrupts(struct otx_cpt_device *cpt) otx_cpt_unregister_interrupts() argument
156 struct otx_cpt_device *cpt = pci_get_drvdata(pdev); otx_cpt_sriov_configure() local
193 struct otx_cpt_device *cpt; otx_cpt_probe() local
262 struct otx_cpt_device *cpt = pci_get_drvdata(pdev); otx_cpt_remove() local
[all...]
H A Dotx_cptpf_mbox.c74 static void otx_cpt_send_msg_to_vf(struct otx_cpt_device *cpt, int vf, in otx_cpt_send_msg_to_vf() argument
78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
86 static void otx_cpt_mbox_send_ack(struct otx_cpt_device *cpt, int vf, in otx_cpt_mbox_send_ack() argument
91 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cpt_mbox_send_ack()
95 static void otx_cptpf_mbox_send_nack(struct otx_cpt_device *cpt, int vf, in otx_cptpf_mbox_send_nack() argument
100 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cptpf_mbox_send_nack()
103 static void otx_cpt_clear_mbox_intr(struct otx_cpt_device *cpt, u32 vf) in otx_cpt_clear_mbox_intr() argument
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
112 static void otx_cpt_cfg_qlen_for_vf(struct otx_cpt_device *cpt, in argument
126 otx_cpt_cfg_vq_priority(struct otx_cpt_device *cpt, int vf, u32 pri) otx_cpt_cfg_vq_priority() argument
135 otx_cpt_bind_vq_to_grp(struct otx_cpt_device *cpt, u8 q, u8 grp) otx_cpt_bind_vq_to_grp() argument
178 otx_cpt_handle_mbox_intr(struct otx_cpt_device *cpt, int vf) otx_cpt_handle_mbox_intr() argument
240 otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx) otx_cpt_mbox_intr_handler() argument
[all...]
H A DMakefile2 obj-$(CONFIG_CRYPTO_DEV_OCTEONTX_CPT) += octeontx-cpt.o octeontx-cptvf.o
4 octeontx-cpt-objs := otx_cptpf_main.o otx_cptpf_mbox.o otx_cptpf_ucode.o
H A Dotx_cptpf.h31 void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx);
32 void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt);
H A Dotx_cptpf_ucode.c177 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_set_ucode_base() local
182 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_set_ucode_base()
198 writeq((u64) dma_addr, cpt->reg_base + in cpt_set_ucode_base()
206 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_detach_and_disable_cores() local
212 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_detach_and_disable_cores()
217 reg = readq(cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
224 writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
233 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); in cpt_detach_and_disable_cores()
242 reg = readq(cpt->reg_base + OTX_CPT_PF_EXE_CTL); in cpt_detach_and_disable_cores()
246 writeq(reg, cpt in cpt_detach_and_disable_cores()
254 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; cpt_attach_and_enable_cores() local
1563 otx_cpt_disable_all_cores(struct otx_cpt_device *cpt) otx_cpt_disable_all_cores() argument
[all...]
H A Dotx_cptvf.h22 #define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY)
/kernel/linux/linux-5.10/drivers/crypto/cavium/cpt/
H A Dcptpf_main.c17 #define DRV_NAME "thunder-cpt"
27 static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask, in cpt_disable_cores() argument
33 struct device *dev = &cpt->pdev->dev; in cpt_disable_cores()
36 coremask = (coremask << cpt->max_se_cores); in cpt_disable_cores()
39 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_disable_cores()
40 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_disable_cores()
43 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); in cpt_disable_cores()
46 grp = cpt_read_csr64(cpt->reg_base, in cpt_disable_cores()
55 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); in cpt_disable_cores()
56 cpt_write_csr64(cpt in cpt_disable_cores()
64 cpt_enable_cores(struct cpt_device *cpt, u64 coremask, u8 type) cpt_enable_cores() argument
78 cpt_configure_group(struct cpt_device *cpt, u8 grp, u64 coremask, u8 type) cpt_configure_group() argument
92 cpt_disable_mbox_interrupts(struct cpt_device *cpt) cpt_disable_mbox_interrupts() argument
98 cpt_disable_ecc_interrupts(struct cpt_device *cpt) cpt_disable_ecc_interrupts() argument
104 cpt_disable_exec_interrupts(struct cpt_device *cpt) cpt_disable_exec_interrupts() argument
110 cpt_disable_all_interrupts(struct cpt_device *cpt) cpt_disable_all_interrupts() argument
117 cpt_enable_mbox_interrupts(struct cpt_device *cpt) cpt_enable_mbox_interrupts() argument
123 cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) cpt_load_microcode() argument
161 do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) do_cpt_init() argument
252 cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) cpt_ucode_load_fw() argument
320 cpt_ucode_load(struct cpt_device *cpt) cpt_ucode_load() argument
341 struct cpt_device *cpt = (struct cpt_device *)cpt_irq; cpt_mbx0_intr_handler() local
348 cpt_reset(struct cpt_device *cpt) cpt_reset() argument
353 cpt_find_max_enabled_cores(struct cpt_device *cpt) cpt_find_max_enabled_cores() argument
362 cpt_check_bist_status(struct cpt_device *cpt) cpt_check_bist_status() argument
372 cpt_check_exe_bist_status(struct cpt_device *cpt) cpt_check_exe_bist_status() argument
382 cpt_disable_all_cores(struct cpt_device *cpt) cpt_disable_all_cores() argument
412 cpt_unload_microcode(struct cpt_device *cpt) cpt_unload_microcode() argument
431 cpt_device_init(struct cpt_device *cpt) cpt_device_init() argument
467 cpt_register_interrupts(struct cpt_device *cpt) cpt_register_interrupts() argument
497 cpt_unregister_interrupts(struct cpt_device *cpt) cpt_unregister_interrupts() argument
503 cpt_sriov_init(struct cpt_device *cpt, int num_vfs) cpt_sriov_init() argument
546 struct cpt_device *cpt; cpt_probe() local
625 struct cpt_device *cpt = pci_get_drvdata(pdev); cpt_remove() local
640 struct cpt_device *cpt = pci_get_drvdata(pdev); cpt_shutdown() local
[all...]
H A Dcptpf_mbox.c8 static void cpt_send_msg_to_vf(struct cpt_device *cpt, int vf, in cpt_send_msg_to_vf() argument
12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), in cpt_send_msg_to_vf()
14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); in cpt_send_msg_to_vf()
20 static void cpt_mbox_send_ack(struct cpt_device *cpt, int vf, in cpt_mbox_send_ack() argument
25 cpt_send_msg_to_vf(cpt, vf, mbx); in cpt_mbox_send_ack()
28 static void cpt_clear_mbox_intr(struct cpt_device *cpt, u32 vf) in cpt_clear_mbox_intr() argument
31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); in cpt_clear_mbox_intr()
37 static void cpt_cfg_qlen_for_vf(struct cpt_device *cpt, int vf, u32 size) in cpt_cfg_qlen_for_vf() argument
41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_qlen_for_vf()
44 cpt_write_csr64(cpt in cpt_cfg_qlen_for_vf()
50 cpt_cfg_vq_priority(struct cpt_device *cpt, int vf, u32 pri) cpt_cfg_vq_priority() argument
59 cpt_bind_vq_to_grp(struct cpt_device *cpt, u8 q, u8 grp) cpt_bind_vq_to_grp() argument
86 cpt_handle_mbox_intr(struct cpt_device *cpt, int vf) cpt_handle_mbox_intr() argument
146 cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx) cpt_mbox_intr_handler() argument
[all...]
H A Dcpt_common.h24 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED)
25 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER)
26 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY)
H A Dcptpf.h43 * cpt device structure
60 void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
/kernel/linux/linux-6.6/drivers/crypto/cavium/cpt/
H A Dcptpf_main.c16 #define DRV_NAME "thunder-cpt"
26 static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask, in cpt_disable_cores() argument
32 struct device *dev = &cpt->pdev->dev; in cpt_disable_cores()
35 coremask = (coremask << cpt->max_se_cores); in cpt_disable_cores()
38 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_disable_cores()
39 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_disable_cores()
42 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); in cpt_disable_cores()
45 grp = cpt_read_csr64(cpt->reg_base, in cpt_disable_cores()
54 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); in cpt_disable_cores()
55 cpt_write_csr64(cpt in cpt_disable_cores()
63 cpt_enable_cores(struct cpt_device *cpt, u64 coremask, u8 type) cpt_enable_cores() argument
77 cpt_configure_group(struct cpt_device *cpt, u8 grp, u64 coremask, u8 type) cpt_configure_group() argument
91 cpt_disable_mbox_interrupts(struct cpt_device *cpt) cpt_disable_mbox_interrupts() argument
97 cpt_disable_ecc_interrupts(struct cpt_device *cpt) cpt_disable_ecc_interrupts() argument
103 cpt_disable_exec_interrupts(struct cpt_device *cpt) cpt_disable_exec_interrupts() argument
109 cpt_disable_all_interrupts(struct cpt_device *cpt) cpt_disable_all_interrupts() argument
116 cpt_enable_mbox_interrupts(struct cpt_device *cpt) cpt_enable_mbox_interrupts() argument
122 cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) cpt_load_microcode() argument
160 do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) do_cpt_init() argument
251 cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) cpt_ucode_load_fw() argument
319 cpt_ucode_load(struct cpt_device *cpt) cpt_ucode_load() argument
340 struct cpt_device *cpt = (struct cpt_device *)cpt_irq; cpt_mbx0_intr_handler() local
347 cpt_reset(struct cpt_device *cpt) cpt_reset() argument
352 cpt_find_max_enabled_cores(struct cpt_device *cpt) cpt_find_max_enabled_cores() argument
361 cpt_check_bist_status(struct cpt_device *cpt) cpt_check_bist_status() argument
371 cpt_check_exe_bist_status(struct cpt_device *cpt) cpt_check_exe_bist_status() argument
381 cpt_disable_all_cores(struct cpt_device *cpt) cpt_disable_all_cores() argument
411 cpt_unload_microcode(struct cpt_device *cpt) cpt_unload_microcode() argument
430 cpt_device_init(struct cpt_device *cpt) cpt_device_init() argument
466 cpt_register_interrupts(struct cpt_device *cpt) cpt_register_interrupts() argument
496 cpt_unregister_interrupts(struct cpt_device *cpt) cpt_unregister_interrupts() argument
502 cpt_sriov_init(struct cpt_device *cpt, int num_vfs) cpt_sriov_init() argument
545 struct cpt_device *cpt; cpt_probe() local
618 struct cpt_device *cpt = pci_get_drvdata(pdev); cpt_remove() local
633 struct cpt_device *cpt = pci_get_drvdata(pdev); cpt_shutdown() local
[all...]
H A Dcptpf_mbox.c8 static void cpt_send_msg_to_vf(struct cpt_device *cpt, int vf, in cpt_send_msg_to_vf() argument
12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), in cpt_send_msg_to_vf()
14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); in cpt_send_msg_to_vf()
20 static void cpt_mbox_send_ack(struct cpt_device *cpt, int vf, in cpt_mbox_send_ack() argument
25 cpt_send_msg_to_vf(cpt, vf, mbx); in cpt_mbox_send_ack()
28 static void cpt_clear_mbox_intr(struct cpt_device *cpt, u32 vf) in cpt_clear_mbox_intr() argument
31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); in cpt_clear_mbox_intr()
37 static void cpt_cfg_qlen_for_vf(struct cpt_device *cpt, int vf, u32 size) in cpt_cfg_qlen_for_vf() argument
41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_qlen_for_vf()
44 cpt_write_csr64(cpt in cpt_cfg_qlen_for_vf()
50 cpt_cfg_vq_priority(struct cpt_device *cpt, int vf, u32 pri) cpt_cfg_vq_priority() argument
59 cpt_bind_vq_to_grp(struct cpt_device *cpt, u8 q, u8 grp) cpt_bind_vq_to_grp() argument
86 cpt_handle_mbox_intr(struct cpt_device *cpt, int vf) cpt_handle_mbox_intr() argument
146 cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx) cpt_mbox_intr_handler() argument
[all...]
H A Dcpt_common.h24 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED)
25 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER)
26 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY)
H A Dcptpf.h43 * cpt device structure
60 void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
/kernel/linux/linux-5.10/arch/parisc/kernel/
H A Dtime.c71 unsigned long cpt = clocktick; in timer_interrupt() local
82 next_tick += cpt; in timer_interrupt()
83 } while (next_tick - now > cpt); in timer_interrupt()
107 while (next_tick - now > cpt) in timer_interrupt()
108 next_tick += cpt; in timer_interrupt()
117 next_tick += cpt; in timer_interrupt()
/kernel/linux/linux-6.6/arch/parisc/kernel/
H A Dtime.c73 unsigned long cpt = clocktick; in timer_interrupt() local
82 next_tick += cpt; in timer_interrupt()
83 } while (next_tick - now > cpt); in timer_interrupt()
106 while (next_tick - now > cpt) in timer_interrupt()
107 next_tick += cpt; in timer_interrupt()
116 next_tick += cpt; in timer_interrupt()
/kernel/linux/linux-5.10/drivers/crypto/
H A DMakefile13 obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
/kernel/linux/linux-6.6/drivers/crypto/
H A DMakefile15 obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
/kernel/linux/linux-5.10/drivers/s390/cio/
H A Ddevice_status.c158 cdev_irb->esw.esw0.erw.cpt = irb->esw.esw0.erw.cpt; in ccw_device_accumulate_esw()

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