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Searched refs:config_base (Results 1 - 25 of 117) sorted by relevance

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/kernel/linux/linux-5.10/arch/arm/kernel/
H A Dperf_event_v7.c902 armv7_pmnc_write_evtsel(idx, hwc->config_base); in armv7pmu_enable_event()
1038 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; in armv7pmu_get_event_idx()
1073 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1078 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1080 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1082 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1085 * Install the filter into config_base as this is used to in armv7pmu_set_event_filter()
1088 event->config_base = config_base; in armv7pmu_set_event_filter()
1303 * hwc->config_base
1415 krait_evt_setup(int idx, u32 config_base) krait_evt_setup() argument
1472 krait_clearpmu(u32 config_base) krait_clearpmu() argument
1762 scorpion_evt_setup(int idx, u32 config_base) scorpion_evt_setup() argument
1805 scorpion_clearpmu(u32 config_base) scorpion_clearpmu() argument
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H A Dperf_event_xscale.c219 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
224 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
279 if (XSCALE_PERFCTR_CCNT == hwc->config_base) { in xscale1pmu_get_event_idx()
568 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
573 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
578 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
583 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
/kernel/linux/linux-6.6/arch/arm/kernel/
H A Dperf_event_v7.c902 armv7_pmnc_write_evtsel(idx, hwc->config_base); in armv7pmu_enable_event()
1038 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; in armv7pmu_get_event_idx()
1073 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1078 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1080 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1082 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1085 * Install the filter into config_base as this is used to in armv7pmu_set_event_filter()
1088 event->config_base = config_base; in armv7pmu_set_event_filter()
1303 * hwc->config_base
1415 krait_evt_setup(int idx, u32 config_base) krait_evt_setup() argument
1472 krait_clearpmu(u32 config_base) krait_clearpmu() argument
1762 scorpion_evt_setup(int idx, u32 config_base) scorpion_evt_setup() argument
1805 scorpion_clearpmu(u32 config_base) scorpion_clearpmu() argument
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H A Dperf_event_xscale.c219 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
224 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
279 if (XSCALE_PERFCTR_CCNT == hwc->config_base) { in xscale1pmu_get_event_idx()
568 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
573 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
578 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
583 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
/kernel/linux/linux-5.10/arch/arm/mach-bcm/
H A Dbcm63xx_smp.c37 unsigned long config_base; in scu_a9_enable() local
47 config_base = scu_a9_get_base(); in scu_a9_enable()
48 if (!config_base) { in scu_a9_enable()
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
56 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
H A Dplatsmp.c49 unsigned long config_base; in scu_a9_enable() local
58 config_base = scu_a9_get_base(); in scu_a9_enable()
59 if (!config_base) { in scu_a9_enable()
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
67 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
/kernel/linux/linux-6.6/arch/arm/mach-bcm/
H A Dbcm63xx_smp.c37 unsigned long config_base; in scu_a9_enable() local
47 config_base = scu_a9_get_base(); in scu_a9_enable()
48 if (!config_base) { in scu_a9_enable()
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
56 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
H A Dplatsmp.c49 unsigned long config_base; in scu_a9_enable() local
58 config_base = scu_a9_get_base(); in scu_a9_enable()
59 if (!config_base) { in scu_a9_enable()
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
67 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
/kernel/linux/linux-5.10/arch/s390/kernel/
H A Dperf_cpum_cf_diag.c208 event->hw.config_base = 0; in __hw_perf_event_init()
210 /* Add all authorized counter sets to config_base. The in __hw_perf_event_init()
221 event->hw.config_base |= cpumf_ctr_ctl[i]; in __hw_perf_event_init()
225 if (!event->hw.config_base) { in __hw_perf_event_init()
235 debug_sprintf_event(cf_diag_dbg, 5, "%s err %d config_base %#lx\n", in __hw_perf_event_init()
236 __func__, err, event->hw.config_base); in __hw_perf_event_init()
536 ctr_set_multiple_enable(&cpuhw->state, hwc->config_base); in cf_diag_start()
539 event->hw.config_base); in cf_diag_start()
540 ctr_set_multiple_start(&cpuhw->state, hwc->config_base); in cf_diag_start()
555 ctr_set_multiple_stop(&cpuhw->state, hwc->config_base); in cf_diag_stop()
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H A Dperf_cpum_cf.c46 switch (hwc->config_base) { in validate_ctr_version()
108 ctrs_state = cpumf_ctr_ctl[hwc->config_base]; in validate_ctr_auth()
263 * set number in the 'config_base'. The counter set number in __hw_perf_event_init()
267 hwc->config_base = set; in __hw_perf_event_init()
399 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
400 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
410 atomic_inc(&cpuhw->ctr_set[hwc->config_base]); in cpumf_pmu_start()
423 if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) in cpumf_pmu_stop()
424 ctr_set_stop(&cpuhw->state, hwc->config_base); in cpumf_pmu_stop()
447 ctr_set_enable(&cpuhw->state, event->hw.config_base); in cpumf_pmu_add()
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/kernel/linux/linux-6.6/drivers/perf/
H A Dapple_m1_cpu_pmu.c86 * but attributes that get stored in hw->config_base.
361 evt = event->hw.config_base & M1_PMU_CFG_EVENT; in m1_pmu_enable_event()
362 user = event->hw.config_base & M1_PMU_CFG_COUNT_USER; in m1_pmu_enable_event()
363 kernel = event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL; in m1_pmu_enable_event()
438 unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT; in m1_pmu_get_event_idx()
525 unsigned long config_base = 0; in m1_pmu_set_event_filter() local
530 config_base |= M1_PMU_CFG_COUNT_KERNEL; in m1_pmu_set_event_filter()
532 config_base |= M1_PMU_CFG_COUNT_USER; in m1_pmu_set_event_filter()
534 event->config_base = config_base; in m1_pmu_set_event_filter()
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H A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
378 reg_writel(val, hwc->config_base); in uncore_start_event_l3c()
385 reg_writel(0, event->hw.config_base); in uncore_stop_event_l3c()
405 val = reg_readl(hwc->config_base); in uncore_start_event_dmc()
408 reg_writel(val, hwc->config_base); in uncore_start_event_dmc()
425 val = reg_readl(hwc->config_base); in uncore_stop_event_dmc()
427 reg_writel(val, hwc->config_base); in uncore_stop_event_dmc()
445 GET_EVENTID(event, emask)), hwc->config_base); in uncore_start_event_ccpi2()
[all...]
H A Darm_pmuv3.c581 armv8pmu_write_evtype(idx - 1, hwc->config_base); in armv8pmu_write_event_type()
585 write_pmccfiltr(hwc->config_base); in armv8pmu_write_event_type()
587 armv8pmu_write_evtype(idx, hwc->config_base); in armv8pmu_write_event_type()
867 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; in armv8pmu_get_event_idx()
920 unsigned long config_base = 0; in armv8pmu_set_event_filter() local
933 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
935 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
937 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
940 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
947 config_base | in armv8pmu_set_event_filter()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
243 switch (hwc->config_base) { in amdgpu_perf_start()
281 switch (hwc->config_base) { in amdgpu_perf_read()
311 switch (hwc->config_base) { in amdgpu_perf_stop()
346 hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF; in amdgpu_perf_add()
349 hwc->config_base = (hwc->config >> in amdgpu_perf_add()
357 switch (hwc->config_base) { in amdgpu_perf_add()
395 switch (hwc->config_base) { in amdgpu_perf_del()
/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
H A Dpcie-tegra194-acpi.c17 void __iomem *config_base; member
31 pcie_ecam->config_base = cfg->win; in tegra194_acpi_init()
99 return pcie_ecam->config_base + where; in tegra194_map_bus()
/kernel/linux/linux-5.10/arch/arm64/kernel/
H A Dperf_event.c592 armv8pmu_write_evtype(idx - 1, hwc->config_base); in armv8pmu_write_event_type()
596 write_sysreg(hwc->config_base, pmccfiltr_el0); in armv8pmu_write_event_type()
598 armv8pmu_write_evtype(idx, hwc->config_base); in armv8pmu_write_event_type()
850 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; in armv8pmu_get_event_idx()
884 unsigned long config_base = 0; in armv8pmu_set_event_filter() local
897 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
899 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
901 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
904 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
911 config_base | in armv8pmu_set_event_filter()
[all...]
/kernel/linux/linux-5.10/drivers/perf/
H A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
378 reg_writel(val, hwc->config_base); in uncore_start_event_l3c()
385 reg_writel(0, event->hw.config_base); in uncore_stop_event_l3c()
405 val = reg_readl(hwc->config_base); in uncore_start_event_dmc()
408 reg_writel(val, hwc->config_base); in uncore_start_event_dmc()
425 val = reg_readl(hwc->config_base); in uncore_stop_event_dmc()
427 reg_writel(val, hwc->config_base); in uncore_stop_event_dmc()
445 GET_EVENTID(event, emask)), hwc->config_base); in uncore_start_event_ccpi2()
[all...]
/kernel/linux/linux-5.10/arch/x86/events/zhaoxin/
H A Dcore.c296 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
305 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_disable_event()
332 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
342 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_enable_event()
/kernel/linux/linux-6.6/arch/x86/events/zhaoxin/
H A Dcore.c296 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
305 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_disable_event()
332 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
342 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_enable_event()
/kernel/linux/linux-5.10/arch/loongarch/kernel/
H A Dperf_event.c276 (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE; in loongarch_pmu_enable_event()
771 hwc->config_base = CSR_PERFCTRL_IE; in __hw_perf_event_init()
778 hwc->config_base |= CSR_PERFCTRL_PLV3; in __hw_perf_event_init()
779 hwc->config_base |= CSR_PERFCTRL_PLV2; in __hw_perf_event_init()
782 hwc->config_base |= CSR_PERFCTRL_PLV0; in __hw_perf_event_init()
785 hwc->config_base |= CSR_PERFCTRL_PLV1; in __hw_perf_event_init()
788 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/kernel/linux/linux-6.6/arch/loongarch/kernel/
H A Dperf_event.c275 (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE; in loongarch_pmu_enable_event()
780 hwc->config_base = CSR_PERFCTRL_IE; in __hw_perf_event_init()
787 hwc->config_base |= CSR_PERFCTRL_PLV3; in __hw_perf_event_init()
788 hwc->config_base |= CSR_PERFCTRL_PLV2; in __hw_perf_event_init()
791 hwc->config_base |= CSR_PERFCTRL_PLV0; in __hw_perf_event_init()
794 hwc->config_base |= CSR_PERFCTRL_PLV1; in __hw_perf_event_init()
797 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/kernel/linux/linux-6.6/arch/s390/kernel/
H A Dperf_cpum_cf.c801 * set number in the 'config_base' as bit mask. in __hw_perf_event_init()
805 hwc->config_base = cpumf_ctr_ctl[set]; in __hw_perf_event_init()
823 if (!(hwc->config_base & cpumf_ctr_info.auth_ctl)) in __hw_perf_event_init()
927 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
928 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
938 hwc->config_base, true); in cpumf_pmu_start()
945 if ((hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_start()
997 if (!(hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_stop()
1010 event->hw.config_base, in cpumf_pmu_stop()
1012 if (cfdiag_diffctr(cpuhw, event->hw.config_base)) in cpumf_pmu_stop()
[all...]
/kernel/linux/linux-5.10/arch/x86/events/amd/
H A Dibs.c311 hwc->config_base = perf_ibs->msr; in perf_ibs_init()
376 rdmsrl(event->hw.config_base, *config); in perf_ibs_event_update()
387 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
389 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
404 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
406 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
462 rdmsrl(hwc->config_base, config); in perf_ibs_stop()
630 msr = hwc->config_base; in perf_ibs_handle_irq()
/kernel/linux/linux-6.6/arch/x86/events/intel/
H A Duncore_discovery.c388 wrmsrl(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
396 wrmsrl(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
439 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in intel_generic_uncore_pci_enable_event()
448 pci_write_config_dword(pdev, hwc->config_base, 0); in intel_generic_uncore_pci_disable_event()
533 writel(hwc->config, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_enable_event()
544 writel(0, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_disable_event()
/kernel/linux/linux-5.10/arch/nds32/kernel/
H A Dperf_event_cpu.c310 unsigned long config_base = 0; in nds32_pmu_set_event_filter() local
324 config_base |= no_user_tracing; in nds32_pmu_set_event_filter()
327 config_base |= no_kernel_tracing; in nds32_pmu_set_event_filter()
330 * Install the filter into config_base as this is used to in nds32_pmu_set_event_filter()
333 event->config_base |= config_base; in nds32_pmu_set_event_filter()
445 hwc->config_base = 0; in nds32_pmu_enable_event()
448 evnum = hwc->config_base; in nds32_pmu_enable_event()
567 unsigned long evtype = hwc->config_base & SOFTWARE_EVENT_MASK; in nds32_pmu_get_event_idx()
817 hwc->config_base in __hw_perf_event_init()
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