| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | 63 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
69 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
75 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
81 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
87 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
93 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
108 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
122 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
125 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
128 cdclk_config->cdclk in i85x_get_cdclk()
453 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) vlv_calc_voltage_level() argument
539 int cdclk = cdclk_config->cdclk; vlv_set_cdclk() local
628 int cdclk = cdclk_config->cdclk; chv_set_cdclk() local
684 bdw_calc_voltage_level(int cdclk) bdw_calc_voltage_level() argument
730 int cdclk = cdclk_config->cdclk; bdw_set_cdclk() local
826 skl_calc_voltage_level(int cdclk) skl_calc_voltage_level() argument
941 skl_cdclk_decimal(int cdclk) skl_cdclk_decimal() argument
1013 int cdclk = cdclk_config->cdclk; skl_set_cdclk() local
1252 bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) bxt_calc_cdclk_pll_vco() argument
1270 bxt_calc_voltage_level(int cdclk) bxt_calc_voltage_level() argument
1275 cnl_calc_voltage_level(int cdclk) cnl_calc_voltage_level() argument
1285 icl_calc_voltage_level(int cdclk) icl_calc_voltage_level() argument
1295 ehl_calc_voltage_level(int cdclk) ehl_calc_voltage_level() argument
1307 tgl_calc_voltage_level(int cdclk) tgl_calc_voltage_level() argument
1531 int cdclk = cdclk_config->cdclk; bxt_set_cdclk() local
1651 int cdclk, vco; bxt_sanitize_cdclk() local
2200 int min_cdclk, cdclk; vlv_modeset_calc_cdclk() local
2227 int min_cdclk, cdclk; bdw_modeset_calc_cdclk() local
2295 int min_cdclk, cdclk, vco; skl_modeset_calc_cdclk() local
2332 int min_cdclk, min_voltage_level, cdclk, vco; bxt_modeset_calc_cdclk() local
[all...] |
| H A D | intel_cdclk.h | 20 u32 cdclk; member
30 * Logical configuration of cdclk (used for all scaling,
37 * Actual configuration of cdclk, can be different from the
42 /* minimum acceptable cdclk for each pipe */
50 /* forced minimum cdclk for glk+ audio w/a */
77 to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
79 to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
|
| H A D | intel_audio.c | 524 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
532 cdclk = i915->cdclk.hw.cdclk; in calc_hblank_early_prog()
539 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
540 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
542 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
551 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
552 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
1085 return dev_priv->cdclk in i915_audio_component_get_cdclk_freq()
[all...] |
| H A D | intel_panel.c | 1498 clock = KHz(dev_priv->cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1516 clock = KHz(dev_priv->cdclk.hw.cdclk); in i965_hz_to_pwm()
|
| H A D | intel_fbc.c | 879 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { in intel_fbc_can_activate()
|
| H A D | intel_dpll_mgr.c | 1776 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in skl_update_dpll_ref_clks()
2345 * Note: DVFS is actually handled via the cdclk code paths, in cnl_ddi_pll_enable()
2363 * Note: DVFS is actually handled via the cdclk code paths, in cnl_ddi_pll_enable()
2389 * Note: DVFS is actually handled via the cdclk code paths, in cnl_ddi_pll_disable()
2407 * Note: DVFS is actually handled via the cdclk code paths, in cnl_ddi_pll_disable()
2847 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in cnl_update_dpll_ref_clks()
4083 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
4101 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
4125 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
4144 * DVFS pre sequence would be here, but in our driver the cdclk cod in icl_pll_disable()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | 78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 int cdclk) in intel_cdclk_calc_voltage_level()
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk in fixed_266mhz_get_cdclk()
100 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) intel_cdclk_calc_voltage_level() argument
499 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) vlv_calc_voltage_level() argument
585 int cdclk = cdclk_config->cdclk; vlv_set_cdclk() local
674 int cdclk = cdclk_config->cdclk; chv_set_cdclk() local
730 bdw_calc_voltage_level(int cdclk) bdw_calc_voltage_level() argument
772 bdw_cdclk_freq_sel(int cdclk) bdw_cdclk_freq_sel() argument
793 int cdclk = cdclk_config->cdclk; bdw_set_cdclk() local
865 skl_calc_voltage_level(int cdclk) skl_calc_voltage_level() argument
980 skl_cdclk_decimal(int cdclk) skl_cdclk_decimal() argument
1048 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, int cdclk, int vco) skl_cdclk_freq_sel() argument
1075 int cdclk = cdclk_config->cdclk; skl_set_cdclk() local
1226 u32 cdclk; global() member
1400 bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) bxt_calc_cdclk_pll_vco() argument
1418 bxt_calc_voltage_level(int cdclk) bxt_calc_voltage_level() argument
1423 icl_calc_voltage_level(int cdclk) icl_calc_voltage_level() argument
1433 ehl_calc_voltage_level(int cdclk) ehl_calc_voltage_level() argument
1445 tgl_calc_voltage_level(int cdclk) tgl_calc_voltage_level() argument
1457 rplu_calc_voltage_level(int cdclk) rplu_calc_voltage_level() argument
1694 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, int cdclk, int vco) bxt_cdclk_cd2x_div_sel() argument
1715 cdclk_squash_waveform(struct drm_i915_private *dev_priv, int cdclk) cdclk_squash_waveform() argument
1852 int cdclk = cdclk_config->cdclk; _bxt_set_cdclk() local
1903 int cdclk = cdclk_config->cdclk; bxt_set_cdclk() local
1983 int cdclk, clock, vco; bxt_sanitize_cdclk() local
2258 intel_pcode_notify(struct drm_i915_private *i915, u8 voltage_level, u8 active_pipe_count, u16 cdclk, bool cdclk_update_valid, bool pipe_count_update_valid) intel_pcode_notify() argument
2366 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; intel_cdclk_pcode_pre_notify() local
2411 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; intel_cdclk_pcode_post_notify() local
2766 int min_cdclk, cdclk; vlv_modeset_calc_cdclk() local
2793 int min_cdclk, cdclk; bdw_modeset_calc_cdclk() local
2857 int min_cdclk, cdclk, vco; skl_modeset_calc_cdclk() local
2890 int min_cdclk, min_voltage_level, cdclk, vco; bxt_modeset_calc_cdclk() local
[all...] |
| H A D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
27 * Logical configuration of cdclk (used for all scaling,
34 * Actual configuration of cdclk, can be different from the
39 /* minimum acceptable cdclk to satisfy bandwidth requirements */
41 /* minimum acceptable cdclk for each pipe */
49 /* forced minimum cdclk for glk+ audio w/a */
80 to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
82 to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
|
| H A D | intel_audio.c | 524 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
532 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
539 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
540 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
542 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
551 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
552 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
984 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struc argument
[all...] |
| H A D | intel_display_driver.c | 86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
89 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
314 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
|
| H A D | hsw_ips.c | 203 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
204 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
206 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
209 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
247 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
|
| H A D | intel_display_core.h | 116 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
276 const struct intel_cdclk_funcs *cdclk; member
325 /* The current hardware cdclk configuration */
328 /* cdclk, divider, and ratio table from bspec */
334 } cdclk; member
|
| H A D | intel_pmdemand.c | 292 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
293 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
348 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
|
| H A D | intel_dp_aux.c | 84 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
|
| H A D | intel_modeset_setup.c | 158 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
678 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
|
| H A D | intel_backlight.c | 1095 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1113 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
|
| H A D | intel_dpll_mgr.c | 1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3831 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
3851 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
3874 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
3891 * DVFS pre sequence would be here, but in our driver the cdclk code in icl_pll_disable()
3945 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
|
| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
109 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
123 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
124 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
|
| H A D | clk-exynos-audss.c | 129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
191 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
193 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
194 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
|
| H A D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_pm_debugfs.c | 396 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
397 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | debugfs_gt_pm.c | 476 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); in frequency_show()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_drv.h | 282 u8 (*calc_voltage_level)(int cdclk);
807 unsigned int cdclk, vco, ref, bypass; member
933 /* The current hardware cdclk configuration */
936 /* cdclk, divider, and ratio table from bspec */
940 } cdclk; member
987 * dpll and cdclk state is protected by connection_mutex
|
| H A D | i915_debugfs.c | 1007 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); in i915_frequency_info()
|