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Searched refs:VMID (Results 1 - 25 of 59) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.h91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.h91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.h116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
189 type VMID
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
543 pr_err("trying to set page table base for wrong VMID\n"); in set_vm_context_page_table_base()
561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
H A Dmes_v11_0.c748 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init()
822 /* set CP_HQD_VMID.VMID = 0. */ in mes_v11_0_queue_init_register()
824 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v11_0_queue_init_register()
837 /* set CP_MQD_CONTROL.VMID=0 */ in mes_v11_0_queue_init_register()
839 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
H A Dmes_v10_1.c668 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v10_1_mqd_init()
747 /* set CP_HQD_VMID.VMID = 0. */
749 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
762 /* set CP_MQD_CONTROL.VMID=0 */
764 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
H A Dgfx_v11_0.c176 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ in gfx11_kiq_map_queues()
2047 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2091 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2166 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2247 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2288 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2370 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2406 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2412 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2771 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
[all...]
H A Damdgpu_amdkfd_gfx_v8.c45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
578 pr_err("trying to set page table base for wrong VMID\n"); in set_vm_context_page_table_base()
H A Dcikd.h59 #define VMID(x) ((x) << 4) macro
H A Dvid.h72 #define VMID(x) ((x) << 4) macro
H A Dgmc_v7_0.c451 * VMID 0 is the physical GPU addresses as used by the kernel.
765 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
1043 * VMID 0 is reserved for System in gmc_v7_0_sw_init()
1291 VMID); in gmc_v7_0_process_interrupt()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.h116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
193 type VMID
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v10_1.c652 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v10_1_mqd_init()
733 /* set CP_HQD_VMID.VMID = 0. */ in mes_v10_1_queue_init_register()
735 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v10_1_queue_init_register()
748 /* set CP_MQD_CONTROL.VMID=0 */ in mes_v10_1_queue_init_register()
750 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v10_1_queue_init_register()
H A Damdgpu_amdkfd_gfx_v7.c94 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
665 pr_err("trying to set page table base for wrong VMID\n"); in set_vm_context_page_table_base()
685 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
H A Dcikd.h59 #define VMID(x) ((x) << 4) macro
H A Dvid.h72 #define VMID(x) ((x) << 4) macro
H A Dgmc_v7_0.c456 * VMID 0 is the physical GPU addresses as used by the kernel.
772 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
1049 * VMID 0 is reserved for System in gmc_v7_0_sw_init()
1298 VMID); in gmc_v7_0_process_interrupt()
H A Damdgpu_amdkfd_gfx_v8.c51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
626 pr_err("trying to set page table base for wrong VMID\n"); in set_vm_context_page_table_base()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dcik_sdma.c964 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
984 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dcik_sdma.c961 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c83 // Program VMID reg in hubp3_program_surface_flip_and_addr()
86 VMID, address->vmid); in hubp3_program_surface_flip_and_addr()
H A Ddcn30_hubp.h237 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c79 // Program VMID reg in hubp3_program_surface_flip_and_addr()
82 VMID, address->vmid); in hubp3_program_surface_flip_and_addr()
H A Ddcn30_hubp.h239 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubp.h224 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\

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