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Searched refs:SCLK_FREQ_SETTING_STEP_0_PART1 (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dr600_dpm.c481 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_post_divider()
488 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_reference_divider()
495 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_feedback_divider()
502 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_step_time()
H A Dr600d.h1362 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dr600_dpm.c481 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_post_divider()
488 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_reference_divider()
495 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_feedback_divider()
502 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_step_time()
H A Dr600d.h1362 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 macro

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