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Searched refs:REG_RXPSEL (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h144 #define REG_RXPSEL 0x808 macro
H A Drtw8822b.c146 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8822b_phy_set_param()
155 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8822b_phy_set_param()
564 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
565 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, in rtw8822b_toggle_igi()
597 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
616 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
777 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); in rtw8822b_config_trx_mode()
H A Drtw8821c.c136 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8821c_phy_set_param()
146 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8821c_phy_set_param()
301 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
323 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
576 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
H A Drtw8821c.h178 #define REG_RXPSEL 0x808 macro
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h152 #define REG_RXPSEL 0x808 macro
H A Drtw8822b.c165 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8822b_phy_set_param()
174 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8822b_phy_set_param()
585 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
586 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, in rtw8822b_toggle_igi()
618 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
637 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
798 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); in rtw8822b_config_trx_mode()
H A Drtw8821c.c184 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8821c_phy_set_param()
194 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8821c_phy_set_param()
391 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
413 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
703 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
H A Drtw8821c.h217 #define REG_RXPSEL 0x808 macro

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