RALINK_PCIEPHY_P0_CTL_OFFSET (reference) in projects: kernel - OpenGrok search results

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Searched refs:RALINK_PCIEPHY_P0_CTL_OFFSET (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/arch/mips/pci/
H A D	pci-mt7620.c	`65 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 macro 270 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET); in mt7628_pci_hw_init()`
/kernel/linux/linux-6.6/arch/mips/pci/
H A D	pci-mt7620.c	`65 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 macro 270 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET); in mt7628_pci_hw_init()`

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