18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci *  Ralink MT7620A SoC PCI support
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
68c2ecf20Sopenharmony_ci *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
78c2ecf20Sopenharmony_ci */
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci#include <linux/types.h>
108c2ecf20Sopenharmony_ci#include <linux/pci.h>
118c2ecf20Sopenharmony_ci#include <linux/io.h>
128c2ecf20Sopenharmony_ci#include <linux/init.h>
138c2ecf20Sopenharmony_ci#include <linux/delay.h>
148c2ecf20Sopenharmony_ci#include <linux/interrupt.h>
158c2ecf20Sopenharmony_ci#include <linux/of.h>
168c2ecf20Sopenharmony_ci#include <linux/of_irq.h>
178c2ecf20Sopenharmony_ci#include <linux/of_pci.h>
188c2ecf20Sopenharmony_ci#include <linux/reset.h>
198c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci#include <asm/mach-ralink/ralink_regs.h>
228c2ecf20Sopenharmony_ci#include <asm/mach-ralink/mt7620.h>
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci#define RALINK_PCI_IO_MAP_BASE		0x10160000
258c2ecf20Sopenharmony_ci#define RALINK_PCI_MEMORY_BASE		0x0
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci#define RALINK_INT_PCIE0		4
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci#define RALINK_CLKCFG1			0x30
308c2ecf20Sopenharmony_ci#define RALINK_GPIOMODE			0x60
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci#define PPLL_CFG1			0x9c
338c2ecf20Sopenharmony_ci#define PPLL_LD				BIT(23)
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci#define PPLL_DRV			0xa0
368c2ecf20Sopenharmony_ci#define PDRV_SW_SET			BIT(31)
378c2ecf20Sopenharmony_ci#define LC_CKDRVPD			BIT(19)
388c2ecf20Sopenharmony_ci#define LC_CKDRVOHZ			BIT(18)
398c2ecf20Sopenharmony_ci#define LC_CKDRVHZ			BIT(17)
408c2ecf20Sopenharmony_ci#define LC_CKTEST			BIT(16)
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci/* PCI Bridge registers */
438c2ecf20Sopenharmony_ci#define RALINK_PCI_PCICFG_ADDR		0x00
448c2ecf20Sopenharmony_ci#define PCIRST				BIT(1)
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci#define RALINK_PCI_PCIENA		0x0C
478c2ecf20Sopenharmony_ci#define PCIINT2				BIT(20)
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci#define RALINK_PCI_CONFIG_ADDR		0x20
508c2ecf20Sopenharmony_ci#define RALINK_PCI_CONFIG_DATA_VIRT_REG	0x24
518c2ecf20Sopenharmony_ci#define RALINK_PCI_MEMBASE		0x28
528c2ecf20Sopenharmony_ci#define RALINK_PCI_IOBASE		0x2C
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci/* PCI RC registers */
558c2ecf20Sopenharmony_ci#define RALINK_PCI0_BAR0SETUP_ADDR	0x10
568c2ecf20Sopenharmony_ci#define RALINK_PCI0_IMBASEBAR0_ADDR	0x18
578c2ecf20Sopenharmony_ci#define RALINK_PCI0_ID			0x30
588c2ecf20Sopenharmony_ci#define RALINK_PCI0_CLASS		0x34
598c2ecf20Sopenharmony_ci#define RALINK_PCI0_SUBID		0x38
608c2ecf20Sopenharmony_ci#define RALINK_PCI0_STATUS		0x50
618c2ecf20Sopenharmony_ci#define PCIE_LINK_UP_ST			BIT(0)
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci#define PCIEPHY0_CFG			0x90
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci#define RALINK_PCIEPHY_P0_CTL_OFFSET	0x7498
668c2ecf20Sopenharmony_ci#define RALINK_PCIE0_CLK_EN		BIT(26)
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci#define BUSY				0x80000000
698c2ecf20Sopenharmony_ci#define WAITRETRY_MAX			10
708c2ecf20Sopenharmony_ci#define WRITE_MODE			(1UL << 23)
718c2ecf20Sopenharmony_ci#define DATA_SHIFT			0
728c2ecf20Sopenharmony_ci#define ADDR_SHIFT			8
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_cistatic void __iomem *bridge_base;
768c2ecf20Sopenharmony_cistatic void __iomem *pcie_base;
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_cistatic struct reset_control *rstpcie0;
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_cistatic inline void bridge_w32(u32 val, unsigned reg)
818c2ecf20Sopenharmony_ci{
828c2ecf20Sopenharmony_ci	iowrite32(val, bridge_base + reg);
838c2ecf20Sopenharmony_ci}
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_cistatic inline u32 bridge_r32(unsigned reg)
868c2ecf20Sopenharmony_ci{
878c2ecf20Sopenharmony_ci	return ioread32(bridge_base + reg);
888c2ecf20Sopenharmony_ci}
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_cistatic inline void pcie_w32(u32 val, unsigned reg)
918c2ecf20Sopenharmony_ci{
928c2ecf20Sopenharmony_ci	iowrite32(val, pcie_base + reg);
938c2ecf20Sopenharmony_ci}
948c2ecf20Sopenharmony_ci
958c2ecf20Sopenharmony_cistatic inline u32 pcie_r32(unsigned reg)
968c2ecf20Sopenharmony_ci{
978c2ecf20Sopenharmony_ci	return ioread32(pcie_base + reg);
988c2ecf20Sopenharmony_ci}
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_cistatic inline void pcie_m32(u32 clr, u32 set, unsigned reg)
1018c2ecf20Sopenharmony_ci{
1028c2ecf20Sopenharmony_ci	u32 val = pcie_r32(reg);
1038c2ecf20Sopenharmony_ci
1048c2ecf20Sopenharmony_ci	val &= ~clr;
1058c2ecf20Sopenharmony_ci	val |= set;
1068c2ecf20Sopenharmony_ci	pcie_w32(val, reg);
1078c2ecf20Sopenharmony_ci}
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_cistatic int wait_pciephy_busy(void)
1108c2ecf20Sopenharmony_ci{
1118c2ecf20Sopenharmony_ci	unsigned long reg_value = 0x0, retry = 0;
1128c2ecf20Sopenharmony_ci
1138c2ecf20Sopenharmony_ci	while (1) {
1148c2ecf20Sopenharmony_ci		reg_value = pcie_r32(PCIEPHY0_CFG);
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ci		if (reg_value & BUSY)
1178c2ecf20Sopenharmony_ci			mdelay(100);
1188c2ecf20Sopenharmony_ci		else
1198c2ecf20Sopenharmony_ci			break;
1208c2ecf20Sopenharmony_ci		if (retry++ > WAITRETRY_MAX) {
1218c2ecf20Sopenharmony_ci			pr_warn("PCIE-PHY retry failed.\n");
1228c2ecf20Sopenharmony_ci			return -1;
1238c2ecf20Sopenharmony_ci		}
1248c2ecf20Sopenharmony_ci	}
1258c2ecf20Sopenharmony_ci	return 0;
1268c2ecf20Sopenharmony_ci}
1278c2ecf20Sopenharmony_ci
1288c2ecf20Sopenharmony_cistatic void pcie_phy(unsigned long addr, unsigned long val)
1298c2ecf20Sopenharmony_ci{
1308c2ecf20Sopenharmony_ci	wait_pciephy_busy();
1318c2ecf20Sopenharmony_ci	pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
1328c2ecf20Sopenharmony_ci		 PCIEPHY0_CFG);
1338c2ecf20Sopenharmony_ci	mdelay(1);
1348c2ecf20Sopenharmony_ci	wait_pciephy_busy();
1358c2ecf20Sopenharmony_ci}
1368c2ecf20Sopenharmony_ci
1378c2ecf20Sopenharmony_cistatic int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
1388c2ecf20Sopenharmony_ci			   int size, u32 *val)
1398c2ecf20Sopenharmony_ci{
1408c2ecf20Sopenharmony_ci	unsigned int slot = PCI_SLOT(devfn);
1418c2ecf20Sopenharmony_ci	u8 func = PCI_FUNC(devfn);
1428c2ecf20Sopenharmony_ci	u32 address;
1438c2ecf20Sopenharmony_ci	u32 data;
1448c2ecf20Sopenharmony_ci	u32 num = 0;
1458c2ecf20Sopenharmony_ci
1468c2ecf20Sopenharmony_ci	if (bus)
1478c2ecf20Sopenharmony_ci		num = bus->number;
1488c2ecf20Sopenharmony_ci
1498c2ecf20Sopenharmony_ci	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
1508c2ecf20Sopenharmony_ci		  (func << 8) | (where & 0xfc) | 0x80000000;
1518c2ecf20Sopenharmony_ci	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
1528c2ecf20Sopenharmony_ci	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
1538c2ecf20Sopenharmony_ci
1548c2ecf20Sopenharmony_ci	switch (size) {
1558c2ecf20Sopenharmony_ci	case 1:
1568c2ecf20Sopenharmony_ci		*val = (data >> ((where & 3) << 3)) & 0xff;
1578c2ecf20Sopenharmony_ci		break;
1588c2ecf20Sopenharmony_ci	case 2:
1598c2ecf20Sopenharmony_ci		*val = (data >> ((where & 3) << 3)) & 0xffff;
1608c2ecf20Sopenharmony_ci		break;
1618c2ecf20Sopenharmony_ci	case 4:
1628c2ecf20Sopenharmony_ci		*val = data;
1638c2ecf20Sopenharmony_ci		break;
1648c2ecf20Sopenharmony_ci	}
1658c2ecf20Sopenharmony_ci
1668c2ecf20Sopenharmony_ci	return PCIBIOS_SUCCESSFUL;
1678c2ecf20Sopenharmony_ci}
1688c2ecf20Sopenharmony_ci
1698c2ecf20Sopenharmony_cistatic int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
1708c2ecf20Sopenharmony_ci			    int size, u32 val)
1718c2ecf20Sopenharmony_ci{
1728c2ecf20Sopenharmony_ci	unsigned int slot = PCI_SLOT(devfn);
1738c2ecf20Sopenharmony_ci	u8 func = PCI_FUNC(devfn);
1748c2ecf20Sopenharmony_ci	u32 address;
1758c2ecf20Sopenharmony_ci	u32 data;
1768c2ecf20Sopenharmony_ci	u32 num = 0;
1778c2ecf20Sopenharmony_ci
1788c2ecf20Sopenharmony_ci	if (bus)
1798c2ecf20Sopenharmony_ci		num = bus->number;
1808c2ecf20Sopenharmony_ci
1818c2ecf20Sopenharmony_ci	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
1828c2ecf20Sopenharmony_ci		  (func << 8) | (where & 0xfc) | 0x80000000;
1838c2ecf20Sopenharmony_ci	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
1848c2ecf20Sopenharmony_ci	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
1858c2ecf20Sopenharmony_ci
1868c2ecf20Sopenharmony_ci	switch (size) {
1878c2ecf20Sopenharmony_ci	case 1:
1888c2ecf20Sopenharmony_ci		data = (data & ~(0xff << ((where & 3) << 3))) |
1898c2ecf20Sopenharmony_ci			(val << ((where & 3) << 3));
1908c2ecf20Sopenharmony_ci		break;
1918c2ecf20Sopenharmony_ci	case 2:
1928c2ecf20Sopenharmony_ci		data = (data & ~(0xffff << ((where & 3) << 3))) |
1938c2ecf20Sopenharmony_ci			(val << ((where & 3) << 3));
1948c2ecf20Sopenharmony_ci		break;
1958c2ecf20Sopenharmony_ci	case 4:
1968c2ecf20Sopenharmony_ci		data = val;
1978c2ecf20Sopenharmony_ci		break;
1988c2ecf20Sopenharmony_ci	}
1998c2ecf20Sopenharmony_ci
2008c2ecf20Sopenharmony_ci	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
2018c2ecf20Sopenharmony_ci
2028c2ecf20Sopenharmony_ci	return PCIBIOS_SUCCESSFUL;
2038c2ecf20Sopenharmony_ci}
2048c2ecf20Sopenharmony_ci
2058c2ecf20Sopenharmony_cistruct pci_ops mt7620_pci_ops = {
2068c2ecf20Sopenharmony_ci	.read	= pci_config_read,
2078c2ecf20Sopenharmony_ci	.write	= pci_config_write,
2088c2ecf20Sopenharmony_ci};
2098c2ecf20Sopenharmony_ci
2108c2ecf20Sopenharmony_cistatic struct resource mt7620_res_pci_mem1;
2118c2ecf20Sopenharmony_cistatic struct resource mt7620_res_pci_io1;
2128c2ecf20Sopenharmony_cistruct pci_controller mt7620_controller = {
2138c2ecf20Sopenharmony_ci	.pci_ops	= &mt7620_pci_ops,
2148c2ecf20Sopenharmony_ci	.mem_resource	= &mt7620_res_pci_mem1,
2158c2ecf20Sopenharmony_ci	.mem_offset	= 0x00000000UL,
2168c2ecf20Sopenharmony_ci	.io_resource	= &mt7620_res_pci_io1,
2178c2ecf20Sopenharmony_ci	.io_offset	= 0x00000000UL,
2188c2ecf20Sopenharmony_ci	.io_map_base	= 0xa0000000,
2198c2ecf20Sopenharmony_ci};
2208c2ecf20Sopenharmony_ci
2218c2ecf20Sopenharmony_cistatic int mt7620_pci_hw_init(struct platform_device *pdev)
2228c2ecf20Sopenharmony_ci{
2238c2ecf20Sopenharmony_ci	/* bypass PCIe DLL */
2248c2ecf20Sopenharmony_ci	pcie_phy(0x0, 0x80);
2258c2ecf20Sopenharmony_ci	pcie_phy(0x1, 0x04);
2268c2ecf20Sopenharmony_ci
2278c2ecf20Sopenharmony_ci	/* Elastic buffer control */
2288c2ecf20Sopenharmony_ci	pcie_phy(0x68, 0xB4);
2298c2ecf20Sopenharmony_ci
2308c2ecf20Sopenharmony_ci	/* put core into reset */
2318c2ecf20Sopenharmony_ci	pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
2328c2ecf20Sopenharmony_ci	reset_control_assert(rstpcie0);
2338c2ecf20Sopenharmony_ci
2348c2ecf20Sopenharmony_ci	/* disable power and all clocks */
2358c2ecf20Sopenharmony_ci	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
2368c2ecf20Sopenharmony_ci	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
2378c2ecf20Sopenharmony_ci
2388c2ecf20Sopenharmony_ci	/* bring core out of reset */
2398c2ecf20Sopenharmony_ci	reset_control_deassert(rstpcie0);
2408c2ecf20Sopenharmony_ci	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
2418c2ecf20Sopenharmony_ci	mdelay(100);
2428c2ecf20Sopenharmony_ci
2438c2ecf20Sopenharmony_ci	if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
2448c2ecf20Sopenharmony_ci		dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
2458c2ecf20Sopenharmony_ci		reset_control_assert(rstpcie0);
2468c2ecf20Sopenharmony_ci		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
2478c2ecf20Sopenharmony_ci		return -1;
2488c2ecf20Sopenharmony_ci	}
2498c2ecf20Sopenharmony_ci
2508c2ecf20Sopenharmony_ci	/* power up the bus */
2518c2ecf20Sopenharmony_ci	rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
2528c2ecf20Sopenharmony_ci		    PPLL_DRV);
2538c2ecf20Sopenharmony_ci
2548c2ecf20Sopenharmony_ci	return 0;
2558c2ecf20Sopenharmony_ci}
2568c2ecf20Sopenharmony_ci
2578c2ecf20Sopenharmony_cistatic int mt7628_pci_hw_init(struct platform_device *pdev)
2588c2ecf20Sopenharmony_ci{
2598c2ecf20Sopenharmony_ci	u32 val = 0;
2608c2ecf20Sopenharmony_ci
2618c2ecf20Sopenharmony_ci	/* bring the core out of reset */
2628c2ecf20Sopenharmony_ci	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
2638c2ecf20Sopenharmony_ci	reset_control_deassert(rstpcie0);
2648c2ecf20Sopenharmony_ci
2658c2ecf20Sopenharmony_ci	/* enable the pci clk */
2668c2ecf20Sopenharmony_ci	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
2678c2ecf20Sopenharmony_ci	mdelay(100);
2688c2ecf20Sopenharmony_ci
2698c2ecf20Sopenharmony_ci	/* voodoo from the SDK driver */
2708c2ecf20Sopenharmony_ci	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
2718c2ecf20Sopenharmony_ci
2728c2ecf20Sopenharmony_ci	pci_config_read(NULL, 0, 0x70c, 4, &val);
2738c2ecf20Sopenharmony_ci	val &= ~(0xff) << 8;
2748c2ecf20Sopenharmony_ci	val |= 0x50 << 8;
2758c2ecf20Sopenharmony_ci	pci_config_write(NULL, 0, 0x70c, 4, val);
2768c2ecf20Sopenharmony_ci
2778c2ecf20Sopenharmony_ci	pci_config_read(NULL, 0, 0x70c, 4, &val);
2788c2ecf20Sopenharmony_ci	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
2798c2ecf20Sopenharmony_ci
2808c2ecf20Sopenharmony_ci	return 0;
2818c2ecf20Sopenharmony_ci}
2828c2ecf20Sopenharmony_ci
2838c2ecf20Sopenharmony_cistatic int mt7620_pci_probe(struct platform_device *pdev)
2848c2ecf20Sopenharmony_ci{
2858c2ecf20Sopenharmony_ci	struct resource *bridge_res = platform_get_resource(pdev,
2868c2ecf20Sopenharmony_ci							    IORESOURCE_MEM, 0);
2878c2ecf20Sopenharmony_ci	struct resource *pcie_res = platform_get_resource(pdev,
2888c2ecf20Sopenharmony_ci							  IORESOURCE_MEM, 1);
2898c2ecf20Sopenharmony_ci	u32 val = 0;
2908c2ecf20Sopenharmony_ci
2918c2ecf20Sopenharmony_ci	rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
2928c2ecf20Sopenharmony_ci	if (IS_ERR(rstpcie0))
2938c2ecf20Sopenharmony_ci		return PTR_ERR(rstpcie0);
2948c2ecf20Sopenharmony_ci
2958c2ecf20Sopenharmony_ci	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
2968c2ecf20Sopenharmony_ci	if (IS_ERR(bridge_base))
2978c2ecf20Sopenharmony_ci		return PTR_ERR(bridge_base);
2988c2ecf20Sopenharmony_ci
2998c2ecf20Sopenharmony_ci	pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
3008c2ecf20Sopenharmony_ci	if (IS_ERR(pcie_base))
3018c2ecf20Sopenharmony_ci		return PTR_ERR(pcie_base);
3028c2ecf20Sopenharmony_ci
3038c2ecf20Sopenharmony_ci	iomem_resource.start = 0;
3048c2ecf20Sopenharmony_ci	iomem_resource.end = ~0;
3058c2ecf20Sopenharmony_ci	ioport_resource.start = 0;
3068c2ecf20Sopenharmony_ci	ioport_resource.end = ~0;
3078c2ecf20Sopenharmony_ci
3088c2ecf20Sopenharmony_ci	/* bring up the pci core */
3098c2ecf20Sopenharmony_ci	switch (ralink_soc) {
3108c2ecf20Sopenharmony_ci	case MT762X_SOC_MT7620A:
3118c2ecf20Sopenharmony_ci		if (mt7620_pci_hw_init(pdev))
3128c2ecf20Sopenharmony_ci			return -1;
3138c2ecf20Sopenharmony_ci		break;
3148c2ecf20Sopenharmony_ci
3158c2ecf20Sopenharmony_ci	case MT762X_SOC_MT7628AN:
3168c2ecf20Sopenharmony_ci	case MT762X_SOC_MT7688:
3178c2ecf20Sopenharmony_ci		if (mt7628_pci_hw_init(pdev))
3188c2ecf20Sopenharmony_ci			return -1;
3198c2ecf20Sopenharmony_ci		break;
3208c2ecf20Sopenharmony_ci
3218c2ecf20Sopenharmony_ci	default:
3228c2ecf20Sopenharmony_ci		dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
3238c2ecf20Sopenharmony_ci		return -1;
3248c2ecf20Sopenharmony_ci	}
3258c2ecf20Sopenharmony_ci	mdelay(50);
3268c2ecf20Sopenharmony_ci
3278c2ecf20Sopenharmony_ci	/* enable write access */
3288c2ecf20Sopenharmony_ci	pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
3298c2ecf20Sopenharmony_ci	mdelay(100);
3308c2ecf20Sopenharmony_ci
3318c2ecf20Sopenharmony_ci	/* check if there is a card present */
3328c2ecf20Sopenharmony_ci	if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
3338c2ecf20Sopenharmony_ci		reset_control_assert(rstpcie0);
3348c2ecf20Sopenharmony_ci		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
3358c2ecf20Sopenharmony_ci		if (ralink_soc == MT762X_SOC_MT7620A)
3368c2ecf20Sopenharmony_ci			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
3378c2ecf20Sopenharmony_ci		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
3388c2ecf20Sopenharmony_ci		return -1;
3398c2ecf20Sopenharmony_ci	}
3408c2ecf20Sopenharmony_ci
3418c2ecf20Sopenharmony_ci	/* setup ranges */
3428c2ecf20Sopenharmony_ci	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
3438c2ecf20Sopenharmony_ci	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
3448c2ecf20Sopenharmony_ci
3458c2ecf20Sopenharmony_ci	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
3468c2ecf20Sopenharmony_ci	pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
3478c2ecf20Sopenharmony_ci	pcie_w32(0x06040001, RALINK_PCI0_CLASS);
3488c2ecf20Sopenharmony_ci
3498c2ecf20Sopenharmony_ci	/* enable interrupts */
3508c2ecf20Sopenharmony_ci	pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
3518c2ecf20Sopenharmony_ci
3528c2ecf20Sopenharmony_ci	/* voodoo from the SDK driver */
3538c2ecf20Sopenharmony_ci	pci_config_read(NULL, 0, 4, 4, &val);
3548c2ecf20Sopenharmony_ci	pci_config_write(NULL, 0, 4, 4, val | 0x7);
3558c2ecf20Sopenharmony_ci
3568c2ecf20Sopenharmony_ci	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
3578c2ecf20Sopenharmony_ci	register_pci_controller(&mt7620_controller);
3588c2ecf20Sopenharmony_ci
3598c2ecf20Sopenharmony_ci	return 0;
3608c2ecf20Sopenharmony_ci}
3618c2ecf20Sopenharmony_ci
3628c2ecf20Sopenharmony_ciint pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
3638c2ecf20Sopenharmony_ci{
3648c2ecf20Sopenharmony_ci	u16 cmd;
3658c2ecf20Sopenharmony_ci	u32 val;
3668c2ecf20Sopenharmony_ci	int irq = 0;
3678c2ecf20Sopenharmony_ci
3688c2ecf20Sopenharmony_ci	if ((dev->bus->number == 0) && (slot == 0)) {
3698c2ecf20Sopenharmony_ci		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
3708c2ecf20Sopenharmony_ci		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
3718c2ecf20Sopenharmony_ci				 RALINK_PCI_MEMORY_BASE);
3728c2ecf20Sopenharmony_ci		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
3738c2ecf20Sopenharmony_ci	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
3748c2ecf20Sopenharmony_ci		irq = RALINK_INT_PCIE0;
3758c2ecf20Sopenharmony_ci	} else {
3768c2ecf20Sopenharmony_ci		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
3778c2ecf20Sopenharmony_ci			dev->bus->number, slot);
3788c2ecf20Sopenharmony_ci		return 0;
3798c2ecf20Sopenharmony_ci	}
3808c2ecf20Sopenharmony_ci	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
3818c2ecf20Sopenharmony_ci		dev->bus->number, slot, irq);
3828c2ecf20Sopenharmony_ci
3838c2ecf20Sopenharmony_ci	/* configure the cache line size to 0x14 */
3848c2ecf20Sopenharmony_ci	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
3858c2ecf20Sopenharmony_ci
3868c2ecf20Sopenharmony_ci	/* configure latency timer to 0xff */
3878c2ecf20Sopenharmony_ci	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
3888c2ecf20Sopenharmony_ci	pci_read_config_word(dev, PCI_COMMAND, &cmd);
3898c2ecf20Sopenharmony_ci
3908c2ecf20Sopenharmony_ci	/* setup the slot */
3918c2ecf20Sopenharmony_ci	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
3928c2ecf20Sopenharmony_ci	pci_write_config_word(dev, PCI_COMMAND, cmd);
3938c2ecf20Sopenharmony_ci	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3948c2ecf20Sopenharmony_ci
3958c2ecf20Sopenharmony_ci	return irq;
3968c2ecf20Sopenharmony_ci}
3978c2ecf20Sopenharmony_ci
3988c2ecf20Sopenharmony_ciint pcibios_plat_dev_init(struct pci_dev *dev)
3998c2ecf20Sopenharmony_ci{
4008c2ecf20Sopenharmony_ci	return 0;
4018c2ecf20Sopenharmony_ci}
4028c2ecf20Sopenharmony_ci
4038c2ecf20Sopenharmony_cistatic const struct of_device_id mt7620_pci_ids[] = {
4048c2ecf20Sopenharmony_ci	{ .compatible = "mediatek,mt7620-pci" },
4058c2ecf20Sopenharmony_ci	{},
4068c2ecf20Sopenharmony_ci};
4078c2ecf20Sopenharmony_ci
4088c2ecf20Sopenharmony_cistatic struct platform_driver mt7620_pci_driver = {
4098c2ecf20Sopenharmony_ci	.probe = mt7620_pci_probe,
4108c2ecf20Sopenharmony_ci	.driver = {
4118c2ecf20Sopenharmony_ci		.name = "mt7620-pci",
4128c2ecf20Sopenharmony_ci		.of_match_table = of_match_ptr(mt7620_pci_ids),
4138c2ecf20Sopenharmony_ci	},
4148c2ecf20Sopenharmony_ci};
4158c2ecf20Sopenharmony_ci
4168c2ecf20Sopenharmony_cistatic int __init mt7620_pci_init(void)
4178c2ecf20Sopenharmony_ci{
4188c2ecf20Sopenharmony_ci	return platform_driver_register(&mt7620_pci_driver);
4198c2ecf20Sopenharmony_ci}
4208c2ecf20Sopenharmony_ci
4218c2ecf20Sopenharmony_ciarch_initcall(mt7620_pci_init);
422