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Searched refs:PP_STATUS (Results 1 - 22 of 22) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dpsb_lid.c30 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
46 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c224 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
324 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
330 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
H A Doaktrail_device.c265 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_save_display_registers()
375 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_restore_display_registers()
380 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_restore_display_registers()
H A Dcdv_intel_lvds.c118 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
129 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
H A Doaktrail_lvds.c49 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
60 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
H A Dcdv_intel_dp.c432 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
433 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
464 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_off()
466 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { in cdv_intel_edp_panel_off()
H A Dpsb_intel_reg.h150 #define PP_STATUS 0x61200 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dpsb_lid.c30 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
46 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c223 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
234 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
322 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
328 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
H A Doaktrail_device.c207 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_save_display_registers()
317 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_restore_display_registers()
322 pp_stat = PSB_RVDC32(PP_STATUS); in oaktrail_restore_display_registers()
H A Doaktrail_lvds.c51 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
62 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
H A Dcdv_intel_lvds.c120 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
131 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
H A Dcdv_intel_dp.c428 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
429 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
460 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_off()
462 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { in cdv_intel_edp_panel_off()
H A Dpsb_intel_reg.h150 #define PP_STATUS 0x61200 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_pps_regs.h21 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) macro
H A Dintel_lvds.c327 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds()
343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
382 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) in intel_lvds_shutdown()
H A Dintel_pps.c275 return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON; in pps_has_pp_on()
495 regs->pp_stat = PP_STATUS(pps_idx); in intel_pps_get_registers()
567 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_check_power_unlocked()
601 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
611 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
753 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_on_unlocked()
825 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_off_sync_unlocked()
1456 * the panel and wait for the PP_STATUS bit to become zero. in pps_init_delays()
H A Dintel_display_power.c1218 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds()
338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
H A Dintel_dp.c984 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
1121 regs->pp_stat = PP_STATUS(pps_idx); in intel_pps_get_registers()
3043 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in edp_panel_vdd_on()
3112 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in edp_panel_vdd_off_sync()
7083 * the panel and wait for the PP_STATUS bit to become zero. in intel_dp_init_panel_power_sequencer()
H A Dintel_display_power.c4824 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_reg.h5004 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) macro

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