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Searched refs:PLL_REF_DIV (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/x86/
H A Dclk-cgu-pll.c18 #define PLL_REF_DIV(x) ((x) + 0x08) macro
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
/kernel/linux/linux-6.6/drivers/clk/x86/
H A Dclk-cgu-pll.c18 #define PLL_REF_DIV(x) ((x) + 0x08) macro
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
148 type PLL_REF_DIV; \
H A Ddce_clock_source.c1447 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1466 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
202 type PLL_REF_DIV; \
H A Ddce_clock_source.c1580 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1599 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
/kernel/linux/linux-5.10/drivers/video/fbdev/aty/
H A Dmach64_ct.c54 * PLL_REF_DIV * POST_DIV
57 * PLL_REF_DIV can be set by the user, but is the same for all clocks.
388 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
514 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
627 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); in aty_resume_pll_ct()
H A Datyfb_base.c2465 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init()
3095 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()
/kernel/linux/linux-6.6/drivers/video/fbdev/aty/
H A Dmach64_ct.c52 * PLL_REF_DIV * POST_DIV
55 * PLL_REF_DIV can be set by the user, but is the same for all clocks.
389 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
515 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
628 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); in aty_resume_pll_ct()
H A Datyfb_base.c2470 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init()
3096 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c85 #define PLL_REF_DIV 0x6b macro
271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider in chipone_configure_pll()
272 * register PLL_REF_DIV[4] is extra 1:2 divider in chipone_configure_pll()
274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider in chipone_configure_pll()
288 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */ in chipone_configure_pll()
295 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */ in chipone_configure_pll()
339 chipone_writeb(icn, PLL_REF_DIV, ref_div); in chipone_configure_pll()
/kernel/linux/linux-5.10/include/video/
H A Dmach64.h782 #define PLL_REF_DIV 0x02 macro
/kernel/linux/linux-6.6/include/video/
H A Dmach64.h782 #define PLL_REF_DIV 0x02 macro

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