Searched refs:PLLU_BASE (Results 1 - 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 74 #define PLLU_BASE 0xc0 macro
2251 .base_reg = PLLU_BASE,
2865 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2870 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2873 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2881 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); in tegra210_enable_pllu()
2897 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2907 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2909 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2929 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
[all...] |
| H A D | clk-tegra114.c | 73 #define PLLU_BASE 0xc0 macro
472 .base_reg = PLLU_BASE,
953 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
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| H A D | clk-tegra30.c | 71 #define PLLU_BASE 0xc0 macro
476 .base_reg = PLLU_BASE,
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| H A D | clk-tegra20.c | 52 #define PLLU_BASE 0xc0 macro
370 .base_reg = PLLU_BASE,
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| H A D | clk-tegra124.c | 52 #define PLLU_BASE 0xc0 macro
735 .base_reg = PLLU_BASE,
1155 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
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| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 74 #define PLLU_BASE 0xc0 macro
2302 .base_reg = PLLU_BASE,
2916 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2921 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2924 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2932 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); in tegra210_enable_pllu()
2948 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2958 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2960 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2980 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
[all...] |
| H A D | clk-tegra114.c | 73 #define PLLU_BASE 0xc0 macro
472 .base_reg = PLLU_BASE,
953 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
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| H A D | clk-tegra30.c | 73 #define PLLU_BASE 0xc0 macro
478 .base_reg = PLLU_BASE,
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| H A D | clk-tegra20.c | 54 #define PLLU_BASE 0xc0 macro
372 .base_reg = PLLU_BASE,
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| H A D | clk-tegra124.c | 52 #define PLLU_BASE 0xc0 macro
735 .base_reg = PLLU_BASE,
1155 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
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