Lines Matching refs:PLLU_BASE
74 #define PLLU_BASE 0xc0
2251 .base_reg = PLLU_BASE,
2865 reg = readl_relaxed(clk_base + PLLU_BASE);
2870 writel(reg, clk_base + PLLU_BASE);
2873 writel(reg, clk_base + PLLU_BASE);
2881 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
2897 reg = readl_relaxed(clk_base + PLLU_BASE);
2907 reg = readl_relaxed(clk_base + PLLU_BASE);
2909 writel(reg, clk_base + PLLU_BASE);
2929 reg = readl_relaxed(clk_base + PLLU_BASE);
2931 writel_relaxed(reg, clk_base + PLLU_BASE);
3222 clk_base + PLLU_BASE, 16, 4, 0,
3251 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3258 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3265 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,