Searched refs:FIFO_CTRL1 (Results 1 - 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/sound/soc/meson/ |
| H A D | axg-frddr.c | 39 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
66 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, in axg_frddr_dai_startup()
153 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
277 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
347 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
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| H A D | axg-toddr.c | 45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
49 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
188 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
248 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
258 static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
318 .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
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| H A D | axg-fifo.c | 188 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_ack_irq()
193 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_ack_irq()
255 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_pcm_open()
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| H A D | axg-fifo.h | 48 #define FIFO_CTRL1 0x04 macro
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| /kernel/linux/linux-6.6/sound/soc/meson/ |
| H A D | axg-toddr.c | 45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
49 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
189 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
250 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
260 static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
321 .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
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| H A D | axg-frddr.c | 40 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
42 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
44 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
62 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, in axg_frddr_dai_hw_params()
168 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
294 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
365 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
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| H A D | axg-fifo.c | 189 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_ack_irq()
194 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_ack_irq()
256 regmap_update_bits(fifo->map, FIFO_CTRL1, in axg_fifo_pcm_open()
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| H A D | axg-fifo.h | 48 #define FIFO_CTRL1 0x04 macro
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