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Help
Searched
refs:DIV0FAULT
(Results
1 - 13
of
13
) sorted by relevance
/kernel/liteos_m/arch/arm/cortex-m3/keil/
H
A
D
los_interrupt.c
168
#define
DIV0FAULT
(1 << 4)
macro
430
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
432
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
H
A
D
los_interrupt.c
170
#define
DIV0FAULT
(1 << 4)
macro
427
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
429
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
H
A
D
los_interrupt.c
170
#define
DIV0FAULT
(1 << 4)
macro
427
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
429
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
H
A
D
los_interrupt.c
169
#define
DIV0FAULT
(1 << 4)
macro
441
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
443
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m4/iar/
H
A
D
los_interrupt.c
169
#define
DIV0FAULT
(1 << 4)
macro
431
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
433
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
H
A
D
los_interrupt.c
169
#define
DIV0FAULT
(1 << 4)
macro
435
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
437
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
H
A
D
los_interrupt.c
170
#define
DIV0FAULT
(1 << 4)
macro
427
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
429
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
H
A
D
los_interrupt.c
168
#define
DIV0FAULT
(1 << 4)
macro
430
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
432
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
);
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
H
A
D
los_interrupt.c
171
#define
DIV0FAULT
(1 << 4)
macro
430
*(volatile UINT32 *)OS_NVIC_CCR |=
DIV0FAULT
;
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
H
A
D
los_interrupt.c
171
#define
DIV0FAULT
(1 << 4)
macro
430
*(volatile UINT32 *)OS_NVIC_CCR |=
DIV0FAULT
;
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
H
A
D
los_interrupt.c
171
#define
DIV0FAULT
(1 << 4)
macro
430
*(volatile UINT32 *)OS_NVIC_CCR |=
DIV0FAULT
;
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
H
A
D
los_interrupt.c
172
#define
DIV0FAULT
(1 << 4)
macro
426
*(volatile UINT32 *)OS_NVIC_CCR |=
DIV0FAULT
;
in HalHwiInit()
/kernel/liteos_m/arch/arm/cortex-m7/iar/
H
A
D
los_interrupt.c
172
#define
DIV0FAULT
(1 << 4)
macro
433
*(volatile UINT32 *)OS_NVIC_CCR |= (
DIV0FAULT
| UNALIGNFAULT);
in HalHwiInit()
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