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Searched refs:AR_CR (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
46 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_powermode_wow_sleep()
47 ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", in ath9k_hw_set_powermode_wow_sleep()
48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
H A Dmac.c706 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_stopdmarecv()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
728 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
H A Dar9002_phy.c560 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9002_hw_tx99_start()
H A Dar9002_mac.c24 REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar9002_hw_rx_enable()
H A Dar9003_mac.c23 REG_WRITE(hw, AR_CR, 0); in ar9003_hw_rx_enable()
H A Dar9003_phy.c1809 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
H A Dreg.h22 #define AR_CR 0x0008 macro
H A Ddebug.c467 seq_printf(file, "AR_CR: 0x%x\n", REG_READ_D(ah, AR_CR)); in read_file_dma()
H A Dhw.c1525 (REG_READ(ah, AR_CR) & AR_CR_RXE)) in ath9k_hw_chip_reset()
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
46 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE(ah), 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_powermode_wow_sleep()
47 ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", in ath9k_hw_set_powermode_wow_sleep()
48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
H A Dmac.c706 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_stopdmarecv()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE(ah)) == 0) in ath9k_hw_stopdmarecv()
728 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
H A Dar9002_phy.c560 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9002_hw_tx99_start()
H A Dar9002_mac.c24 REG_WRITE(ah, AR_CR, AR_CR_RXE(ah)); in ar9002_hw_rx_enable()
H A Dar9003_mac.c23 REG_WRITE(hw, AR_CR, 0); in ar9003_hw_rx_enable()
H A Dreg.h22 #define AR_CR 0x0008 macro
H A Ddebug.c452 seq_printf(file, "AR_CR: 0x%x\n", REG_READ_D(ah, AR_CR)); in read_file_dma()
H A Dar9003_phy.c1800 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
H A Dhw.c1524 (REG_READ(ah, AR_CR) & AR_CR_RXE(ah))) in ath9k_hw_chip_reset()

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