Searched refs:write_csi2_dphy_reg_mask (Results 1 - 2 of 2) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 269 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw, int index, u32 value, u32 mask)
in write_csi2_dphy_reg_mask() function
810 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_THS_SETTLE, hsfreq, 0x1ff);
in csi2_dcphy_hw_stream_on()
811 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_ERR_SOT_SYNC, sot_sync, 0xff);
in csi2_dcphy_hw_stream_on()
814 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_THS_SETTLE, hsfreq, 0x1ff);
in csi2_dcphy_hw_stream_on()
815 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_ERR_SOT_SYNC, sot_sync, 0xff);
in csi2_dcphy_hw_stream_on()
818 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_THS_SETTLE, hsfreq, 0x1ff);
in csi2_dcphy_hw_stream_on()
819 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_ERR_SOT_SYNC, sot_sync, 0xff);
in csi2_dcphy_hw_stream_on()
822 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_THS_SETTLE, hsfreq, 0x1ff);
in csi2_dcphy_hw_stream_on()
823 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_ERR_SOT_SYNC, sot_sync, 0xff);
in csi2_dcphy_hw_stream_on()
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 269 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw, in write_csi2_dphy_reg_mask() function
816 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_THS_SETTLE, hsfreq, 0x1ff); in csi2_dcphy_hw_stream_on()
817 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_ERR_SOT_SYNC, sot_sync, 0xff); in csi2_dcphy_hw_stream_on()
820 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_THS_SETTLE, hsfreq, 0x1ff); in csi2_dcphy_hw_stream_on()
821 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_ERR_SOT_SYNC, sot_sync, 0xff); in csi2_dcphy_hw_stream_on()
824 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_THS_SETTLE, hsfreq, 0x1ff); in csi2_dcphy_hw_stream_on()
825 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_ERR_SOT_SYNC, sot_sync, 0xff); in csi2_dcphy_hw_stream_on()
828 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_THS_SETTLE, hsfreq, 0x1ff); in csi2_dcphy_hw_stream_on()
829 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_ERR_SOT_SYNC, sot_sync, 0xff); in csi2_dcphy_hw_stream_on()
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