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Searched refs:watchdog (Results 1 - 7 of 7) sorted by relevance

/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/wtdg/
H A DMakefile64 @mkdir -p $(REL_INC) && cp -f watchdog.h $(REL_INC)/
71 @rm -f $(REL_INC)/watchdog.h
89 @mkdir -p $(REL_INC) && cp -f watchdog.h $(REL_INC)/
94 @rm -f $(REL_INC)/watchdog.h
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dpcie_core.c67 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
78 /* Disable/restore ASPM Control to protect the watchdog reset */ in pcie_watchdog_reset()
85 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), wd_mask, wd_val); in pcie_watchdog_reset()
86 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), WD_COUNTER_MASK, 4); in pcie_watchdog_reset()
96 si_corereg_writeonly(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4); in pcie_watchdog_reset()
107 * cause shadow registers are cleared out after watchdog reset. in pcie_watchdog_reset()
H A Dsiutils.c203 static uint32 wd_msticks; /**< watchdog timer ticks normalized to ms */
2022 /** set chip watchdog reset timer to fire in 'ticks' */
2057 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks); in si_watchdog()
2061 /** trigger watchdog reset after ms milliseconds */
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/include/
H A Dhi_sal.h21 #include <watchdog.h>
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Ddbus.h392 void (*watchdog)(void *cbarg); member
H A Dsbchipc.h6 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
229 uint32 watchdog; /* 0x80 */ member
1095 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */
/device/soc/rockchip/common/sdk_linux/kernel/sched/
H A Drt.c2665 static void watchdog(struct rq *rq, struct task_struct *p) in watchdog() function
2688 static inline void watchdog(struct rq *rq, struct task_struct *p) in watchdog() function
2708 watchdog(rq, p); in task_tick_rt()

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