Searched refs:set_rate (Results 1 - 19 of 19) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 107 .set_rate = rockchip_ddrclk_sip_set_rate,
156 .set_rate = rockchip_ddrclk_scpi_set_rate,
213 .set_rate = rockchip_ddrclk_sip_set_rate_v2,
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| H A D | clk-half-divider.c | 135 .set_rate = clk_half_divider_set_rate,
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| H A D | clk-pll.c | 371 * The calling set_rate function is responsible for making sure the
638 .set_rate = rockchip_rk3036_pll_set_rate,
853 .set_rate = rockchip_rk3066_pll_set_rate,
1108 .set_rate = rockchip_rk3399_pll_set_rate,
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 155 .set_rate = clk_virtual_set_rate,
259 .set_rate = vop2_clk_div_set_rate,
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| H A D | dw-dp.c | 654 phy_cfg.dp.set_rate = false; in dw_dp_link_train_update_vs_emph()
686 phy_cfg.dp.set_rate = true; in dw_dp_link_configure()
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| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 171 .set_rate = clk_virtual_set_rate,
276 .set_rate = vop2_clk_div_set_rate,
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| H A D | dw-dp.c | 669 phy_cfg.dp.set_rate = false; in dw_dp_link_train_update_vs_emph()
700 phy_cfg.dp.set_rate = true; in dw_dp_link_configure()
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-dclk-divider.c | 78 .set_rate = clk_dclk_set_rate,
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-dclk-divider.c | 77 .set_rate = clk_dclk_set_rate,
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| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-naneng-edp.c | 154 if (dp->set_rate) {
in rockchip_edp_phy_verify_config()
211 if (opts->dp.set_rate) {
in rockchip_edp_phy_configure()
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| H A D | phy-rockchip-usbdp.c | 731 if (dp->set_rate) {
in rockchip_dp_phy_verify_config()
790 if (opts->dp.set_rate && cfg->dp_phy_set_rate) {
in rockchip_dp_phy_configure()
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| H A D | phy-rockchip-inno-hdmi-phy.c | 732 .set_rate = inno_hdmi_phy_clk_set_rate,
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-naneng-edp.c | 175 if (dp->set_rate) { in rockchip_edp_phy_verify_config()
231 if (opts->dp.set_rate) { in rockchip_edp_phy_configure()
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| H A D | phy-rockchip-usbdp.c | 780 if (dp->set_rate) { in rockchip_dp_phy_verify_config()
837 if (opts->dp.set_rate && cfg->dp_phy_set_rate) { in rockchip_dp_phy_configure()
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| H A D | phy-rockchip-samsung-hdptx.c | 454 if (dp->set_rate) { in rockchip_hdptx_phy_verify_config()
695 if (opts->dp.set_rate) { in rockchip_hdptx_phy_configure()
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| H A D | phy-rockchip-inno-hdmi-phy.c | 627 .set_rate = inno_hdmi_phy_clk_set_rate,
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| H A D | phy-rockchip-samsung-hdptx-hdmi.c | 1963 .set_rate = hdptx_phy_clk_set_rate,
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_reg.c | 586 phy_cfg.dp.set_rate = true; in analogix_dp_set_link_bandwidth()
630 phy_cfg.dp.set_rate = false; in analogix_dp_set_lane_count()
673 phy_cfg.dp.set_rate = false; in analogix_dp_set_lane_link_training()
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| /device/soc/rockchip/common/sdk_linux/include/linux/ |
| H A D | clk-provider.h | 150 * @set_rate: Change the rate of this clock. The requested rate is specified
153 * which is likely helpful for most .set_rate implementation.
164 * separately via calls to .set_parent and .set_rate.
236 int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate);
member
533 * .recalc_rate, .set_rate and .round_rate
819 * Implements .recalc_rate, .set_rate and .round_rate
903 * Implements .recalc_rate, .set_rate and .round_rate
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