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Searched refs:rate (Results 1 - 25 of 116) sorted by relevance

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/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-pll.c115 int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate) in rockchip_pll_clk_rate_to_scale() argument
133 if (rate >= rate_table[i].rate) { in rockchip_pll_clk_rate_to_scale()
161 return rate_table[i].rate; in rockchip_pll_clk_scale_to_rate()
340 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
346 if (rate == rate_table[i].rate) { in rockchip_get_pll_settings()
348 pll->scaling = rate; in rockchip_get_pll_settings()
358 return rockchip_rk3066_pll_clk_set_by_auto(pll, 0x18 * MHZ, rate); in rockchip_get_pll_settings()
360 return rockchip_pll_clk_set_by_auto(pll, 0x18 * MHZ, rate); in rockchip_get_pll_settings()
444 rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3036_pll_get_params() argument
490 rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3036_pll_set_params() argument
547 const struct rockchip_pll_rate_table *rate; rockchip_rk3036_pll_set_rate() local
589 const struct rockchip_pll_rate_table *rate; rockchip_rk3036_pll_init() local
664 rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3066_pll_get_params() argument
705 rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3066_pll_set_params() argument
760 const struct rockchip_pll_rate_table *rate; rockchip_rk3066_pll_set_rate() local
816 const struct rockchip_pll_rate_table *rate; rockchip_rk3066_pll_init() local
898 rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3399_pll_get_params() argument
946 rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3399_pll_set_params() argument
1009 const struct rockchip_pll_rate_table *rate; rockchip_rk3399_pll_set_rate() local
1059 const struct rockchip_pll_rate_table *rate; rockchip_rk3399_pll_init() local
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H A Dclk-half-divider.c13 static bool _is_best_half_div(unsigned long rate, unsigned long now, unsigned long best, unsigned long flags) in _is_best_half_div() argument
16 return abs(rate - now) <= abs(rate - best); in _is_best_half_div()
19 return now <= rate && now >= best; in _is_best_half_div()
34 static int clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, u8 width, in clk_half_divider_bestdiv() argument
41 if (!rate) { in clk_half_divider_bestdiv()
42 rate = 1; in clk_half_divider_bestdiv()
49 bestdiv = DIV_ROUND_UP_ULL(((u64)parent_rate * 0x2), rate); in clk_half_divider_bestdiv()
61 * unsigned long in rate * i below in clk_half_divider_bestdiv()
63 if (rate in clk_half_divider_bestdiv()
87 clk_half_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_half_divider_round_rate() argument
97 clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_half_divider_set_rate() argument
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H A Dclk-cpu.c15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
72 unsigned long rate) in rockchip_get_cpuclk_settings()
78 if (rate in rockchip_get_cpuclk_settings()
71 rockchip_get_cpuclk_settings(struct rockchip_cpuclk *cpuclk, unsigned long rate) rockchip_get_cpuclk_settings() argument
101 rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, const struct rockchip_cpuclk_rate_table *rate) rockchip_cpuclk_set_dividers() argument
121 const struct rockchip_cpuclk_rate_table *rate; rockchip_cpuclk_pre_rate_change() local
181 const struct rockchip_cpuclk_rate_table *rate; rockchip_cpuclk_post_rate_change() local
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H A Dclk-ddr.c85 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_sip_round_rate() argument
89 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0, ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, 0, 0, 0, 0, &res); in rockchip_ddrclk_sip_round_rate()
146 static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_scpi_round_rate() argument
148 rate = rate / MHZ; in rockchip_ddrclk_scpi_round_rate()
149 rate = (rate / DDR_RATE) * DDR_RATE; in rockchip_ddrclk_scpi_round_rate()
151 return (rate * MHZ); in rockchip_ddrclk_scpi_round_rate()
193 static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_sip_round_rate_v2() argument
200 p->hz = rate; in rockchip_ddrclk_sip_round_rate_v2()
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c74 * the rate of the dclk from the soc.
136 return (unsigned long)vop2_clk->rate; in clk_virtual_recalc_rate()
139 static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in clk_virtual_round_rate() argument
143 vop2_clk->rate = rate; in clk_virtual_round_rate()
145 return rate; in clk_virtual_round_rate()
148 static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) in clk_virtual_set_rate() argument
179 cru_dbg("%s %ld(min: %ld max: %ld)\n", clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate); in vop2_clk_mux_determine_rate()
191 static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate) in vop2_div_get_val() argument
195 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in vop2_div_get_val()
205 unsigned long rate; vop2_clk_div_recalc_rate() local
216 vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) vop2_clk_div_round_rate() argument
243 vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) vop2_clk_div_set_rate() argument
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/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c85 * the rate of the dclk from the soc.
150 return (unsigned long)vop2_clk->rate; in clk_virtual_recalc_rate()
153 static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, in clk_virtual_round_rate() argument
158 vop2_clk->rate = rate; in clk_virtual_round_rate()
160 return rate; in clk_virtual_round_rate()
163 static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate, in clk_virtual_set_rate() argument
197 clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate); in vop2_clk_mux_determine_rate()
209 static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate) in vop2_div_get_val() argument
213 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in vop2_div_get_val()
224 unsigned long rate; vop2_clk_div_recalc_rate() local
235 vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) vop2_clk_div_round_rate() argument
259 vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) vop2_clk_div_set_rate() argument
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/device/soc/rockchip/common/sdk_linux/drivers/tty/serial/8250/
H A D8250_dw.c295 unsigned long rate; in dw8250_clk_work_cb() local
297 rate = clk_get_rate(d->clk); in dw8250_clk_work_cb()
298 if (rate <= 0) { in dw8250_clk_work_cb()
304 serial8250_update_uartclk(&up->port, rate); in dw8250_clk_work_cb()
316 * the clk and tty-port mutexes lock. It happens if clock rate change in dw8250_clk_notifier_cb()
350 long rate; in dw8250_set_termios() local
360 rate = 0x16e3600; in dw8250_set_termios()
362 rate = baud * 0x20; in dw8250_set_termios()
364 rate = baud * 0x20; in dw8250_set_termios()
366 rate in dw8250_set_termios()
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/device/soc/hisilicon/hi3516dv300/sdk_linux/sample/taurus/ai_sample/ext_util/
H A Dmisc_util.c34 int IntZoomTo(int n, double rate, double rateMin, double rateMax) in IntZoomTo() argument
43 if (rate > rateMax) { in IntZoomTo()
45 } else if (rate < rateMin) { in IntZoomTo()
48 ret = (int)(n * rate); in IntZoomTo()
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c28 static long clk_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in clk_dclk_round_rate() argument
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
38 *prate = div * rate; in clk_dclk_round_rate()
39 return rate; in clk_dclk_round_rate()
42 static int clk_dclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) in clk_dclk_set_rate() argument
49 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in clk_dclk_set_rate()
H A Dclk-pvtm.c46 unsigned long rate; member
137 /* set pvtm_div to get rate */ in rockchip_clock_pvtm_init_freq()
138 div = DIV_ROUND_UP(0x3e8 * pvtm_cnt, pvtm->rate); in rockchip_clock_pvtm_init_freq()
144 pr_debug("set div %d, rate %luKHZ\n", div, pvtm->rate); in rockchip_clock_pvtm_init_freq()
223 u32 rate; in rockchip_clock_pvtm_probe() local
249 if (!of_property_read_u32(np, "pvtm-rate", &rate)) { in rockchip_clock_pvtm_probe()
250 pvtm->rate = rate; in rockchip_clock_pvtm_probe()
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/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c27 static long clk_dclk_round_rate(struct clk_hw *hw, unsigned long rate, in clk_dclk_round_rate() argument
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
37 *prate = div * rate; in clk_dclk_round_rate()
38 return rate; in clk_dclk_round_rate()
41 static int clk_dclk_set_rate(struct clk_hw *hw, unsigned long rate, in clk_dclk_set_rate() argument
49 value = divider_get_val(rate, parent_rate, divider->table, in clk_dclk_set_rate()
H A Dclk-pvtm.c47 unsigned long rate; member
138 /* set pvtm_div to get rate */ in rockchip_clock_pvtm_init_freq()
139 div = DIV_ROUND_UP(1000 * pvtm_cnt, pvtm->rate); in rockchip_clock_pvtm_init_freq()
145 pr_debug("set div %d, rate %luKHZ\n", div, pvtm->rate); in rockchip_clock_pvtm_init_freq()
227 u32 rate; in rockchip_clock_pvtm_probe() local
248 if (!of_property_read_u32(np, "pvtm-rate", &rate)) in rockchip_clock_pvtm_probe()
249 pvtm->rate = rate; in rockchip_clock_pvtm_probe()
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/device/soc/rockchip/common/sdk_linux/include/soc/rockchip/
H A Dscpi.h30 int scpi_clk_set_val(u16 clk_id, unsigned long rate);
42 int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
55 static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate) in scpi_clk_set_val() argument
110 static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type) in scpi_ddr_set_clk_rate() argument
/device/soc/rockchip/rk3588/kernel/include/soc/rockchip/
H A Dscpi.h30 int scpi_clk_set_val(u16 clk_id, unsigned long rate);
43 int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
56 static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate) in scpi_clk_set_val() argument
112 static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type) in scpi_ddr_set_clk_rate() argument
/device/board/hisilicon/hispark_taurus/audio_drivers/soc/src/
H A Dhi3516_dai_ops.c202 uint32_t rate = device->devData->pcmInfo.rate; in SetIISRate() local
210 if (AiaoGetMclk(rate, &mclkSel) != HDF_SUCCESS) { in SetIISRate()
225 if (AiaoSetSysCtlRegValue(mclkSel, bitWidth, rate, &bclkRegVal) != HDF_SUCCESS) { in SetIISRate()
302 if (DaiCheckSampleRate(param->rate) != HDF_SUCCESS) { in Hi3516DaiHwParams()
319 data->pcmInfo.rate = param->rate; in Hi3516DaiHwParams()
H A Dhi3516_aiao_impl.c423 static int32_t AiaoGetBclkFsclk(const uint32_t fsBit, const uint32_t rate, in AiaoGetBclkFsclk() argument
448 if ((mclkRateNum % (fsBit * rate)) != 0) { in AiaoGetBclkFsclk()
453 ret = AiaoGetBclkSel(mclkRateNum / (fsBit * rate), bclkSel); in AiaoGetBclkFsclk()
464 int32_t AiaoGetMclk(uint32_t rate, uint32_t *mclkSel) in AiaoGetMclk() argument
470 switch (rate) { in AiaoGetMclk()
495 AUDIO_DEVICE_LOG_ERR("not support this sample rate\n"); in AiaoGetMclk()
514 int32_t AiaoSetSysCtlRegValue(uint32_t mclkSel, uint32_t bitWidth, uint32_t rate, uint32_t *clkRegVal) in AiaoSetSysCtlRegValue() argument
528 ret = AiaoGetBclkFsclk(fsBit, rate, mclkSel, &bclkSel, &lrClkSel); in AiaoSetSysCtlRegValue()
/device/board/hisilicon/hispark_taurus/audio_drivers/codec/tfa9879/src/
H A Dtfa9879_codec_ops.c164 static int32_t Tfa9879FrequencyParse(uint32_t rate, uint16_t *freq) in Tfa9879FrequencyParse() argument
170 switch (rate) { in Tfa9879FrequencyParse()
208 AUDIO_DRIVER_LOG_ERR("rate: %d is not support.", rate); in Tfa9879FrequencyParse()
268 ret = Tfa9879FrequencyParse(param->rate, &frequency); in Tfa9879DaiHwParams()
286 AUDIO_DEVICE_LOG_DEBUG("channels = %d, rate = %d, periodSize = %d, \ in Tfa9879DaiHwParams()
288 param->channels, param->rate, param->periodSize, in Tfa9879DaiHwParams()
/device/board/hisilicon/hispark_taurus/audio_drivers/unittest/src/
H A Dhi3516_aiao_impl_test.c284 uint32_t rate = SAMPLERATE; in TestAiaoGetMclk() local
288 ret = AiaoGetMclk(rate, mclkSel); in TestAiaoGetMclk()
302 uint32_t rate = SAMPLERATE; in TestAiaoSetSysCtlRegValue() local
307 ret = AiaoSetSysCtlRegValue(mclkSel, bitWidth, rate, &clkRegVal); in TestAiaoSetSysCtlRegValue()
/device/board/hisilicon/hispark_taurus/audio_drivers/codec/hi3516/src/
H A Dhi3516_codec_impl.c115 static unsigned int CodecGetI2sFs(const unsigned int rate) in CodecGetI2sFs() argument
117 switch (rate) { in CodecGetI2sFs()
134 AUDIO_DEVICE_LOG_DEBUG("unsupport samplerate %d\n", rate); in CodecGetI2sFs()
139 static unsigned int CodecGetAdcModeSel(const unsigned int rate) in CodecGetAdcModeSel() argument
141 switch (rate) { in CodecGetAdcModeSel()
156 AUDIO_DEVICE_LOG_DEBUG("unsupport samplerate %d.\n", rate); in CodecGetAdcModeSel()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/tests/mali_kutf_clk_rate_trace/kernel/
H A Dmali_kutf_clk_rate_trace_test.c59 * @previous_rate: Snapshot start point clock rate.
60 * @current_rate: End point clock rate. It becomes the start rate of the
63 * write is a rate of higher value than the last.
65 * is a rate of lower value than the last.
77 * @listener: Clock rate change listener structure.
241 unsigned long rate; in kutf_clk_trace_do_get_rate() local
256 rate = kbdev->pm.clk_rtm.clks[i]->clock_val; in kutf_clk_trace_do_get_rate()
258 rate = data->snapshot[i].current_rate; in kutf_clk_trace_do_get_rate()
265 rate, idl in kutf_clk_trace_do_get_rate()
805 unsigned long rate; mali_kutf_clk_rate_trace_create_fixture() local
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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-hdmi-phy.c453 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate) in inno_hdmi_phy_get_tmdsclk() argument
460 tmdsclk = (u32)rate / 0x02; in inno_hdmi_phy_get_tmdsclk()
463 tmdsclk = (u32)rate * 0x05 / 0x08; in inno_hdmi_phy_get_tmdsclk()
466 tmdsclk = (u32)rate * 0x03 / 0x04; in inno_hdmi_phy_get_tmdsclk()
469 tmdsclk = (u32)rate * 0x05 / 0x04; in inno_hdmi_phy_get_tmdsclk()
472 tmdsclk = (u32)rate * 0x03 / 0x02; in inno_hdmi_phy_get_tmdsclk()
475 tmdsclk = (u32)rate * 0x02; in inno_hdmi_phy_get_tmdsclk()
478 tmdsclk = rate; in inno_hdmi_phy_get_tmdsclk()
532 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate);
652 static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigne argument
693 inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) inno_hdmi_phy_clk_set_rate() argument
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c367 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate) in inno_hdmi_phy_get_tmdsclk() argument
374 tmdsclk = (u32)rate / 2; in inno_hdmi_phy_get_tmdsclk()
377 tmdsclk = (u32)rate * 5 / 8; in inno_hdmi_phy_get_tmdsclk()
380 tmdsclk = (u32)rate * 3 / 4; in inno_hdmi_phy_get_tmdsclk()
383 tmdsclk = (u32)rate * 5 / 4; in inno_hdmi_phy_get_tmdsclk()
386 tmdsclk = (u32)rate * 3 / 2; in inno_hdmi_phy_get_tmdsclk()
389 tmdsclk = (u32)rate * 2; in inno_hdmi_phy_get_tmdsclk()
392 tmdsclk = rate; in inno_hdmi_phy_get_tmdsclk()
440 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
554 static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, in inno_hdmi_phy_clk_round_rate() argument
590 inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) inno_hdmi_phy_clk_set_rate() argument
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/device/board/hisilicon/hispark_taurus/audio_drivers/dsp/src/
H A Ddsp_ops.c53 static int32_t DspCfgI2sFrequency(uint32_t rate, uint16_t *frequency) in DspCfgI2sFrequency() argument
60 switch (rate) { in DspCfgI2sFrequency()
98 AUDIO_DRIVER_LOG_ERR("rate: %d is not support.", rate); in DspCfgI2sFrequency()
149 ret = DspCfgI2sFrequency(param->rate, &frequency); in DspDaiHwParams()
169 AUDIO_DRIVER_LOG_DEBUG("DspDaiHwParams: channels = %d, rate = %d, periodSize = %d, \ in DspDaiHwParams()
171 param->channels, param->rate, param->periodSize, in DspDaiHwParams()
/device/board/hihope/rk3568/audio_drivers/codec/rk809_codec/src/
H A Drk809_codec_impl.c176 static const RK809SampleRateTimes RK809GetSRT(const uint32_t rate) in RK809GetSRT() argument
178 switch (rate) { in RK809GetSRT()
190 AUDIO_DEVICE_LOG_DEBUG("unsupport samplerate %d\n", rate); in RK809GetSRT()
195 static const RK809PLLInputCLKPreDIV RK809GetPremode(const uint32_t rate) in RK809GetPremode() argument
197 switch (rate) { in RK809GetPremode()
209 AUDIO_DEVICE_LOG_DEBUG("unsupport samplerate %d\n", rate); in RK809GetPremode()
520 codecDaiParamsVal.frequencyVal = param->rate; in Rk809DaiHwParams()
/device/board/hisilicon/hispark_taurus/audio_drivers/soc/include/
H A Dhi3516_aiao_impl.h129 int32_t AiaoGetMclk(uint32_t rate, uint32_t *mclkSel);
131 uint32_t rate, uint32_t *clkRegVal);

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