| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 139 static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in clk_virtual_round_rate() argument
211 cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate); in vop2_clk_div_recalc_rate()
216 static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in vop2_clk_div_round_rate() argument
221 if (*prate < rate) { in vop2_clk_div_round_rate()
222 *prate = rate; in vop2_clk_div_round_rate()
224 if ((*prate >> vop2_clk->div.width) > rate) { in vop2_clk_div_round_rate()
225 *prate = rate; in vop2_clk_div_round_rate()
228 if ((*prate % rate)) { in vop2_clk_div_round_rate()
229 *prate = rate; in vop2_clk_div_round_rate()
233 if (*prate < PLL_RATE_MI in vop2_clk_div_round_rate()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 154 unsigned long *prate) in clk_virtual_round_rate()
230 cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate); in vop2_clk_div_recalc_rate()
236 unsigned long *prate) in vop2_clk_div_round_rate()
241 if (*prate < rate) in vop2_clk_div_round_rate()
242 *prate = rate; in vop2_clk_div_round_rate()
243 if ((*prate >> vop2_clk->div.width) > rate) in vop2_clk_div_round_rate()
244 *prate = rate; in vop2_clk_div_round_rate()
246 if ((*prate % rate)) in vop2_clk_div_round_rate()
247 *prate = rate; in vop2_clk_div_round_rate()
250 if (*prate < PLL_RATE_MI in vop2_clk_div_round_rate()
153 clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_virtual_round_rate() argument
235 vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) vop2_clk_div_round_rate() argument
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 63 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) in rockchip_ddrclk_sip_set_rate() argument
85 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_sip_round_rate() argument
114 static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) in rockchip_ddrclk_scpi_set_rate() argument
146 static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_scpi_round_rate() argument
161 static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw, unsigned long drate, unsigned long prate) in rockchip_ddrclk_sip_set_rate_v2() argument
193 static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in rockchip_ddrclk_sip_round_rate_v2() argument
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| H A D | clk-pll.c | 364 static long rockchip_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) in rockchip_pll_round_rate() argument
461 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in rockchip_rk3036_pll_recalc_rate() argument
465 u64 rate64 = prate, frac_rate64 = prate; in rockchip_rk3036_pll_recalc_rate()
544 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) in rockchip_rk3036_pll_set_rate() argument
549 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
679 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in rockchip_rk3066_pll_recalc_rate() argument
683 u64 rate64 = prate; in rockchip_rk3066_pll_recalc_rate()
689 return prate; in rockchip_rk3066_pll_recalc_rate()
757 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) in rockchip_rk3066_pll_set_rate() argument
917 rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) rockchip_rk3399_pll_recalc_rate() argument
1006 rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) rockchip_rk3399_pll_set_rate() argument
1480 rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate) rockchip_boost_add_core_div() argument
[all...] |
| H A D | clk-half-divider.c | 87 static long clk_half_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in clk_half_divider_round_rate() argument
92 div = clk_half_divider_bestdiv(hw, rate, prate, divider->width, divider->flags); in clk_half_divider_round_rate()
94 return DIV_ROUND_UP_ULL(((u64)*prate * 0x2), div * 0x2 + 0x3); in clk_half_divider_round_rate()
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| H A D | clk.h | 399 void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate);
409 unsigned long prate; member
587 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate) \
592 .gate_offset = (go), .gate_shift = (gs), .gate_flags = (gf), .max_prate = (prate), \
595 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
600 .gate_offset = (go), .gate_shift = (gs), .gate_flags = (gf), .child = (ch), .max_prate = (prate), \
603 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
608 .gate_offset = -1, .child = (ch), .max_prate = (prate), \
728 #define COMPOSITE_DCLK(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw, df, go, gs, gf, prate) \
733 .gate_shift = (gs), .gate_flags = (gf), .max_prate = (prate), \
[all...] |
| H A D | clk-cpu.c | 78 if (rate == rate_table[i].prate) { in rockchip_get_cpuclk_settings()
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| H A D | clk-rk3368.c | 214 .prate = (_prate), \
224 .prate = (_prate), \
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| H A D | clk-rk3188.c | 134 .prate = (_prate), \
169 .prate = (_prate), \
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| H A D | clk-rk3036.c | 98 .prate = (_prate), \
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| H A D | clk-rk3128.c | 98 .prate = (_prate), \
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| H A D | clk-rk3328.c | 111 .prate = (_prate), \
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| H A D | clk-rv1108.c | 85 .prate = (_prate), \
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| H A D | clk-rk3228.c | 99 .prate = (_prate), \
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| H A D | clk-rk3399.c | 325 .prate = _prate##U, \
335 .prate = _prate##U, \
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| H A D | clk-rk3308.c | 73 .prate = (_prate), \
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-dclk-divider.c | 28 static long clk_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) in clk_dclk_round_rate() argument
38 *prate = div * rate; in clk_dclk_round_rate()
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| H A D | clk-rk1808.c | 97 .prate = (_prate), \
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-dclk-divider.c | 28 unsigned long *prate) in clk_dclk_round_rate()
37 *prate = div * rate; in clk_dclk_round_rate()
27 clk_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_dclk_round_rate() argument
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| H A D | clk.h | 480 void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate);
490 unsigned long prate; member
807 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
822 .max_prate = prate, \
825 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
841 .max_prate = prate, \
844 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
858 .max_prate = prate, \
1129 df, go, gs, gf, prate) \
1147 .max_prate = prate, \
[all...] |
| H A D | clk-rk3588.c | 203 .prate = _prate##U, \
216 .prate = _prate##U, \
229 .prate = _prate##U, \
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| /device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/ |
| H A D | clk.h | 480 void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate);
490 unsigned long prate; member
807 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
822 .max_prate = prate, \
825 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
841 .max_prate = prate, \
844 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
858 .max_prate = prate, \
1129 df, go, gs, gf, prate) \
1147 .max_prate = prate, \
[all...] |
| /device/soc/rockchip/common/sdk_linux/include/linux/ |
| H A D | clk-provider.h | 590 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
592 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
1038 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
in divider_round_rate() argument
1041 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags);
in divider_round_rate()
1044 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
in divider_ro_round_rate() argument
1048 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val);
in divider_ro_round_rate()
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 1419 unsigned long prate, unsigned long rate, in samsung_mipi_dcphy_pll_round_rate()
1437 fin = div64_ul(prate, USEC_PER_SEC); in samsung_mipi_dcphy_pll_round_rate()
1744 unsigned long prate = clk_get_rate(samsung->ref_clk); in samsung_mipi_dcphy_pll_calc_rate() local
1752 fout = samsung_mipi_dcphy_pll_round_rate(samsung, prate, rate, in samsung_mipi_dcphy_pll_calc_rate()
1757 __func__, prate, rate); in samsung_mipi_dcphy_pll_calc_rate()
1418 samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, unsigned long prate, unsigned long rate, u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler) samsung_mipi_dcphy_pll_round_rate() argument
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| /device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-dsidphy.c | 312 unsigned long prate = clk_get_rate(inno->ref_clk);
in inno_dsidphy_pll_calc_rate() local
325 fref = prate / PRATE_DIV_TWO;
in inno_dsidphy_pll_calc_rate()
|