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Searched refs:mux_uart3_p (Results 1 - 6 of 6) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3368.c139 PNAME(mux_uart3_p) = {"uart3_src", "uart3_frac", "xin24m"}; variable
263 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
H A Dclk-rk3308.c111 PNAME(mux_uart3_p) = {"clk_uart3_src", "dummy", "clk_uart3_frac"}; variable
182 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
H A Dclk-rk3288.c161 PNAME(mux_uart3_p) = {"uart3_src", "uart3_frac", "xin24m"}; variable
217 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
H A Dclk-px30.c132 PNAME(mux_uart3_p) = {"clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac"}; variable
194 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
H A Dclk-rk3399.c201 PNAME(mux_uart3_p) = {"xin24m", "clk_uart3_div", "clk_uart3_frac"}; variable
266 SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c148 PNAME(mux_uart3_p) = {"clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac", "xin24m"}; variable
201 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);

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