| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 136 PNAME(mux_uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; variable
159 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3128.c | 147 PNAME(mux_uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; variable
182 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3368.c | 138 PNAME(mux_uart2_p) = {"uart2_src", "xin24m"}; variable
358 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
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| H A D | clk-rk3328.c | 162 PNAME(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m"}; variable
208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
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| H A D | clk-rv1108.c | 125 PNAME(mux_uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; variable
164 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 155 PNAME(mux_uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; variable
193 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 110 PNAME(mux_uart2_p) = {"clk_uart2_src", "dummy", "clk_uart2_frac"}; variable
179 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
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| H A D | clk-rk3288.c | 160 PNAME(mux_uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; variable
214 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-px30.c | 131 PNAME(mux_uart2_p) = {"clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac"}; variable
191 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
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| H A D | clk-rk3399.c | 200 PNAME(mux_uart2_p) = {"xin24m", "clk_uart2_div", "clk_uart2_frac"}; variable
263 SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 147 PNAME(mux_uart2_p) = {"clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m"}; variable
198 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
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