| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 135 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
156 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3128.c | 146 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
179 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3368.c | 137 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
260 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
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| H A D | clk-rk3328.c | 161 PNAME(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m"}; variable
205 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
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| H A D | clk-rv1108.c | 124 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
161 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 154 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 109 PNAME(mux_uart1_p) = {"clk_uart1_src", "dummy", "clk_uart1_frac"}; variable
176 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
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| H A D | clk-rk3288.c | 159 PNAME(mux_uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; variable
211 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-px30.c | 130 PNAME(mux_uart1_p) = {"clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac"}; variable
188 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
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| H A D | clk-rk3399.c | 199 PNAME(mux_uart1_p) = {"xin24m", "clk_uart1_div", "clk_uart1_frac"}; variable
260 SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 146 PNAME(mux_uart1_p) = {"clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m"}; variable
195 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
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