| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 134 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
153 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
|
| H A D | clk-rk3128.c | 145 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
176 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
|
| H A D | clk-rk3368.c | 136 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
257 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
|
| H A D | clk-rk3328.c | 160 PNAME(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m"}; variable
202 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
|
| H A D | clk-rv1108.c | 123 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
158 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
|
| H A D | clk-rk3228.c | 153 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
187 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
|
| H A D | clk-rk3308.c | 108 PNAME(mux_uart0_p) = {"clk_uart0_src", "dummy", "clk_uart0_frac"}; variable
173 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
|
| H A D | clk-rk3288.c | 158 PNAME(mux_uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; variable
208 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
|
| H A D | clk-rk3399.c | 198 PNAME(mux_uart0_p) = {"xin24m", "clk_uart0_div", "clk_uart0_frac"}; variable
257 SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
|