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Searched refs:mux_pll_src_cpll_gpll_upll_p (Results 1 - 1 of 1) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3399.c117 PNAME(mux_pll_src_cpll_gpll_upll_p) = {"dummy_cpll", "gpll", "upll"}; variable
151 PNAME(mux_pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"}; variable
527 MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),

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