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/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dspinand.h47 static void hisnfc100_set_system_clock(int clock, int clk_en) in hisnfc100_set_system_clock() argument
52 if (!clock) in hisnfc100_set_system_clock()
53 clock = SPI_NAND_CLK_SEL_75M; in hisnfc100_set_system_clock()
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
66 static void hisnfc100_get_best_clock(unsigned int *clock) in hisnfc100_get_best_clock() argument
81 if (*clock < sysclk[ix]) in hisnfc100_get_best_clock()
85 *clock = clk_reg; in hisnfc100_get_best_clock()
H A Dspinor.h50 static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) in hisfc350_set_system_clock() argument
56 if (clock) { in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
72 static inline void hisfc350_get_best_clock(unsigned int *clock) in hisfc350_get_best_clock() argument
88 if (*clock < sysclk[ix]) in hisfc350_get_best_clock()
93 *clock = clk_reg; in hisfc350_get_best_clock()
H A Dflash.h35 /* SDR/DDR clock */
42 /* Only DDR clock */
158 static inline void hifmc100_set_system_clock(unsigned clock, int clk_en) in hifmc100_set_system_clock() argument
166 if (clock) in hifmc100_set_system_clock()
167 regval |= clock & FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
185 static inline void hifmc100_get_best_clock(unsigned int *clock) in hifmc100_get_best_clock() argument
205 if (*clock < sys_2X_clk[ix]) in hifmc100_get_best_clock()
211 *clock = clk_reg; in hifmc100_get_best_clock()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dspinand.h47 static void hisnfc100_set_system_clock(int clock, int clk_en) in hisnfc100_set_system_clock() argument
52 if (!clock) in hisnfc100_set_system_clock()
53 clock = SPI_NAND_CLK_SEL_75M; in hisnfc100_set_system_clock()
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
66 static void hisnfc100_get_best_clock(unsigned int *clock) in hisnfc100_get_best_clock() argument
81 if (*clock < sysclk[ix]) in hisnfc100_get_best_clock()
85 *clock = clk_reg; in hisnfc100_get_best_clock()
H A Dspinor.h50 static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) in hisfc350_set_system_clock() argument
56 if (clock) { in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
72 static inline void hisfc350_get_best_clock(unsigned int *clock) in hisfc350_get_best_clock() argument
88 if (*clock < sysclk[ix]) in hisfc350_get_best_clock()
93 *clock = clk_reg; in hisfc350_get_best_clock()
H A Dflash.h35 /* SDR/DDR clock */
42 /* Only DDR clock */
158 static inline void hifmc100_set_system_clock(unsigned clock, int clk_en) in hifmc100_set_system_clock() argument
166 if (clock) in hifmc100_set_system_clock()
167 regval |= clock & FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
185 static inline void hifmc100_get_best_clock(unsigned int *clock) in hifmc100_get_best_clock() argument
205 if (*clock < sys_2X_clk[ix]) in hifmc100_get_best_clock()
211 *clock = clk_reg; in hifmc100_get_best_clock()
/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Dmpp_time.h44 * Note when clock is create it is default disabled user need to call enable
45 * fucntion with enable = 1 to enable the clock.
46 * User can use enable function with enable = 0 to disable the clock.
49 void mpp_clock_put(MppClock clock);
50 void mpp_clock_enable(MppClock clock, RK_U32 enable);
54 * start : let clock start timing counter
55 * pause : let clock pause and return the diff to start time
56 * reset : let clock counter to all zero
58 RK_S64 mpp_clock_start(MppClock clock);
59 RK_S64 mpp_clock_pause(MppClock clock);
[all...]
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Dmpp_time.h42 void mpp_clock_put(MppClock clock);
43 void mpp_clock_enable(MppClock clock, RK_U32 enable);
44 RK_S64 mpp_clock_start(MppClock clock);
45 RK_S64 mpp_clock_pause(MppClock clock);
46 RK_S64 mpp_clock_reset(MppClock clock);
47 RK_S64 mpp_clock_get_sum(MppClock clock);
48 RK_S64 mpp_clock_get_count(MppClock clock);
49 const char *mpp_clock_get_name(MppClock clock);
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Dmpp_time.h45 * Note when clock is create it is default disabled user need to call enable
46 * fucntion with enable = 1 to enable the clock.
47 * User can use enable function with enable = 0 to disable the clock.
50 void mpp_clock_put(MppClock clock);
51 void mpp_clock_enable(MppClock clock, RK_U32 enable);
55 * start : let clock start timing counter
56 * pause : let clock pause and return the diff to start time
57 * reset : let clock counter to all zero
59 RK_S64 mpp_clock_start(MppClock clock);
60 RK_S64 mpp_clock_pause(MppClock clock);
[all...]
/device/soc/rockchip/common/hardware/mpp/include/
H A Dmpp_time.h42 void mpp_clock_put(MppClock clock);
43 void mpp_clock_enable(MppClock clock, unsigned int enable);
44 RK_S64 mpp_clock_start(MppClock clock);
45 RK_S64 mpp_clock_pause(MppClock clock);
46 RK_S64 mpp_clock_reset(MppClock clock);
47 RK_S64 mpp_clock_get_sum(MppClock clock);
48 RK_S64 mpp_clock_get_count(MppClock clock);
49 const char *mpp_clock_get_name(MppClock clock);
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/panel/
H A Dpanel-simple.c978 .clock = 71100,
1005 .clock = 9000,
1030 .clock = 33333,
1080 .clock = 51450,
1129 .clock = 72000,
1153 .clock = 69300,
1183 .clock = 70589,
1214 .clock = 69500,
1237 .clock = 150660,
1296 .clock
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_dvfs_policy.c96 if (((int)(gpu_clk->item[i].clock) - target_clock_mhz) > 0) { in mali_pickup_closest_avail_clock()
101 /* If the target clock greater than the maximum clock just pick the maximum one */ in mali_pickup_closest_avail_clock()
164 /* Get current clock value */ in mali_dvfs_policy_realize()
188 /* 2. Calculate target clock if the GPU clock can be tuned */ in mali_dvfs_policy_realize()
195 target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util * mali_desired_fps / in mali_dvfs_policy_realize()
200 target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util / under_perform_boundary_value; in mali_dvfs_policy_realize()
215 gpu_clk->item[clock_step].clock, gpu_clk->item[clock_step].vol / VOL_MILLI, 0, 0, in mali_dvfs_policy_realize()
245 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_DATA, ("mali gpu clock inf in mali_dvfs_policy_init()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_dvfs_policy.c85 if (((int)(gpu_clk->item[i].clock) - target_clock_mhz) > 0) { in mali_pickup_closest_avail_clock()
90 /* If the target clock greater than the maximum clock just pick the maximum one*/ in mali_pickup_closest_avail_clock()
151 /* Get current clock value */ in mali_dvfs_policy_realize()
175 /* 2. Calculate target clock if the GPU clock can be tuned */ in mali_dvfs_policy_realize()
182 target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util * mali_desired_fps / under_perform_boundary_value / current_fps; in mali_dvfs_policy_realize()
186 target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util / under_perform_boundary_value; in mali_dvfs_policy_realize()
202 gpu_clk->item[clock_step].clock, in mali_dvfs_policy_realize()
234 MALI_DEBUG_PRINT(5, ("mali gpu clock inf in mali_dvfs_policy_init()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/platform/rk/
H A Dmali_kbase_config_rk.c322 struct clk *clock = kbdev->clocks[i]; in rk_pm_enable_clk() local
324 if (!clock) { in rk_pm_enable_clk()
325 W("no mali clock control, no need to enable."); in rk_pm_enable_clk()
328 err = clk_enable(clock); in rk_pm_enable_clk()
343 struct clk *clock = kbdev->clocks[i]; in rk_pm_disable_clk() local
345 if (!clock) { in rk_pm_disable_clk()
346 W("no mali clock control, no need to disable."); in rk_pm_disable_clk()
349 clk_disable(clock); in rk_pm_disable_clk()
/device/soc/rockchip/common/sdk_linux/drivers/mmc/host/
H A Dsdhci-of-dwcmshc.c151 static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) in dwcmshc_rk_set_clock() argument
160 if (clock == 0) { in dwcmshc_rk_set_clock()
165 if (clock <= 0x61a80) { in dwcmshc_rk_set_clock()
166 clock = 0x5b8d8; in dwcmshc_rk_set_clock()
169 err = clk_set_rate(pltfm_host->clk, clock); in dwcmshc_rk_set_clock()
171 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); in dwcmshc_rk_set_clock()
174 sdhci_set_clock(host, clock); in dwcmshc_rk_set_clock()
181 if (clock <= 0x3197500) { in dwcmshc_rk_set_clock()
182 /* Disable DLL and reset both of sample and drive clock */ in dwcmshc_rk_set_clock()
[all...]
H A Ddw_mmc-rockchip.c48 if (ios->clock == 0) { in dw_mci_rk3288_set_ios()
53 * cclkin: source clock of mmc controller in dw_mci_rk3288_set_ios()
54 * bus_hz: card interface clock generated by CLKGEN in dw_mci_rk3288_set_ios()
56 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
61 if (ios->clock < priv->f_min) { in dw_mci_rk3288_set_ios()
62 ios->clock = priv->f_min; in dw_mci_rk3288_set_ios()
66 cclkin = RK3288_CLKGEN_MUL * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
68 cclkin = ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
73 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); in dw_mci_rk3288_set_ios()
94 * different output clock delay in dw_mci_rk3288_set_ios()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_kernel_linux.c308 /* Lets User space read cpu clock cycles */ in mali_init_cpu_time_counters()
312 /** A timer function that configures the cycle clock counter on current CPU.
350 /** Init the performance registers on all CPUs to count clock cycles.
352 * If \a print_only is 1, it will intead print the current clock value of all CPUs.
459 mali_gpu_clk[0].clock, in mali_module_init()
561 /*Initilization clock and regulator*/ in mali_probe()
576 /* Need to name the gpu clock "clk_mali" in the device tree */ in mali_probe()
577 mdev->clock = clk_get(mdev->dev, "clk_mali"); in mali_probe()
578 if (IS_ERR_OR_NULL(mdev->clock)) { in mali_probe()
579 MALI_DEBUG_PRINT(2, ("Continuing without Mali clock contro in mali_probe()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_kernel_linux.c308 /* Lets User space read cpu clock cycles */ in mali_init_cpu_time_counters()
312 /** A timer function that configures the cycle clock counter on current CPU.
351 /** Init the performance registers on all CPUs to count clock cycles.
353 * If \a print_only is 1, it will intead print the current clock value of all CPUs.
467 mali_gpu_clk[0].clock, mali_gpu_clk[0].vol / 0x3e8, 0, 0, 0); in mali_module_init()
561 /* Initilization clock and regulator */ in mali_probe()
576 /* Need to name the gpu clock "clk_mali" in the device tree */ in mali_probe()
577 mdev->clock = clk_get(mdev->dev, "clk_mali"); in mali_probe()
578 if (IS_ERR_OR_NULL(mdev->clock)) { in mali_probe()
579 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_INFORMATOIN, ("Continuing without Mali clock contro in mali_probe()
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/adc/
H A Dhi_adc.c63 hi_xtal_clock clock = hi_get_xtal_clock(); in hi_adc_read() local
66 if (clock == HI_XTAL_CLOCK_24M) { in hi_adc_read()
68 } else if (clock == HI_XTAL_CLOCK_40M) { in hi_adc_read()
/device/soc/hisilicon/common/platform/mmc/himci_v200/proc/
H A Dhimci_proc.c122 static uint32_t ProcAnalyzeClockScale(uint32_t clock, uint32_t *val) in ProcAnalyzeClockScale() argument
125 uint32_t tmp = clock; in ProcAnalyzeClockScale()
209 static int32_t ProcStatsClkPrint(uint32_t clock, struct SeqBuf *s) in ProcStatsClkPrint() argument
221 clockScale = ProcAnalyzeClockScale(clock, &clockValue); in ProcStatsClkPrint()
222 status = LosBufPrintf(s, "\tHost work clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
227 status = LosBufPrintf(s, "\tCard support clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
232 status = LosBufPrintf(s, "\tCard work clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
284 status = ProcStatsClkPrint(card->workPara.clock, s); in ProcStatsCardInfoPrint()
/device/soc/hisilicon/common/platform/mmc/sdhci/proc/
H A Dsdhci_proc.c121 static uint32_t ProcAnalyzeClockScale(uint32_t clock, uint32_t *val) in ProcAnalyzeClockScale() argument
124 uint32_t tmp = clock; in ProcAnalyzeClockScale()
208 static int32_t ProcStatsClkPrint(uint32_t clock, struct SeqBuf *s) in ProcStatsClkPrint() argument
220 clockScale = ProcAnalyzeClockScale(clock, &clockValue); in ProcStatsClkPrint()
221 status = LosBufPrintf(s, "\tHost work clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
226 status = LosBufPrintf(s, "\tCard support clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
231 status = LosBufPrintf(s, "\tCard work clock: %d%s\n", clockValue, clockUnit[clockScale]); in ProcStatsClkPrint()
283 status = ProcStatsClkPrint(card->workPara.clock, s); in ProcStatsCardInfoPrint()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_modes.c321 /* 15/13. Find pixel clock frequency (kHz for xf86) */ in drm_cvt_mode()
325 tmp -= drm_mode->clock % CVT_CLOCK_STEP; in drm_cvt_mode()
326 drm_mode->clock = tmp; in drm_cvt_mode()
496 /* 21.Find pixel clock frequency: */ in drm_gtf_mode_complex()
521 drm_mode->clock = pixel_freq; in drm_gtf_mode_complex()
600 dmode->clock = vm->pixelclock / 0x3e8; in drm_display_mode_from_videomode()
645 vm->pixelclock = dmode->clock * 0x3e8; in drm_display_mode_to_videomode()
778 num = mode->clock; in drm_mode_vrefresh()
835 p->crtc_clock = p->clock; in drm_mode_set_crtcinfo()
950 * do clock chec in drm_mode_match_clock()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/platform/rk/
H A Dmali_kbase_config_rk.c373 struct clk *clock = kbdev->clocks[i]; in rk_pm_enable_clk() local
375 if (!clock) { in rk_pm_enable_clk()
376 W("no mali clock control, no need to enable."); in rk_pm_enable_clk()
379 err = clk_enable(clock); in rk_pm_enable_clk()
393 struct clk *clock = kbdev->clocks[i]; in rk_pm_disable_clk() local
395 if (!clock) { in rk_pm_disable_clk()
396 W("no mali clock control, no need to disable."); in rk_pm_disable_clk()
399 clk_disable(clock); in rk_pm_disable_clk()
/device/soc/hisilicon/common/platform/mmc/sdhci/
H A Dsdhci.c152 host->clock = 0; in SdhciDoReset()
616 static uint32_t SdhciSelectClock(struct SdhciHost *host, uint32_t clock) in SdhciSelectClock() argument
627 if (host->hostId == 1 && (clock > SDHCI_MMC_FREQ_50M)) { in SdhciSelectClock()
628 HDF_LOGE("host%u doesn't support freq %u!", host->hostId, clock); in SdhciSelectClock()
632 if (clock >= SDHCI_MMC_FREQ_150M) { in SdhciSelectClock()
635 } else if (clock >= SDHCI_MMC_FREQ_112P5M) { in SdhciSelectClock()
638 } else if (clock >= SDHCI_MMC_FREQ_90M) { in SdhciSelectClock()
641 } else if (clock >= SDHCI_MMC_FREQ_50M) { in SdhciSelectClock()
644 } else if (clock >= SDHCI_MMC_FREQ_25M) { in SdhciSelectClock()
647 } else if (clock > in SdhciSelectClock()
888 SdhciSetClock(struct MmcCntlr *cntlr, uint32_t clock) SdhciSetClock() argument
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/platform/rk/
H A Dmali_kbase_config_rk.c313 if (!(kbdev->clock)) { in rk_pm_enable_clk()
314 W("no mali clock control, no need to enable."); in rk_pm_enable_clk()
317 err = clk_enable(kbdev->clock); in rk_pm_enable_clk()
328 if (!(kbdev->clock)) { in rk_pm_disable_clk()
329 W("no mali clock control, no need to disable."); in rk_pm_disable_clk()
332 clk_disable(kbdev->clock); in rk_pm_disable_clk()

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