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/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/libcoap/include/coap2/
H A Dbits.h2 * bits.h -- bit vector manipulation
21 * Sets the bit @p bit in bit-vector @p vec. This function returns @c 1 if bit
22 * was set or @c -1 on error (i.e. when the given bit does not fit in the
25 * @param vec The bit-vector to change.
27 * @param bit The bit to set in @p vec.
29 * @return @c -1 if @p bit doe
32 bits_setb(uint8_t *vec, size_t size, uint8_t bit) bits_setb() argument
52 bits_clrb(uint8_t *vec, size_t size, uint8_t bit) bits_clrb() argument
71 bits_getb(const uint8_t *vec, size_t size, uint8_t bit) bits_getb() argument
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_osk_bitops.h23 MALI_STATIC_INLINE void _mali_internal_clear_bit(u32 bit, u32 *addr) in _mali_internal_clear_bit() argument
25 MALI_DEBUG_ASSERT(bit < 32); in _mali_internal_clear_bit()
28 (*addr) &= ~(1 << bit); in _mali_internal_clear_bit()
31 MALI_STATIC_INLINE void _mali_internal_set_bit(u32 bit, u32 *addr)
33 MALI_DEBUG_ASSERT(bit < 32);
36 (*addr) |= (1 << bit);
39 MALI_STATIC_INLINE u32 _mali_internal_test_bit(u32 bit, u32 value)
41 MALI_DEBUG_ASSERT(bit < 32);
42 return value & (1 << bit);
58 negated = (u32) - inverted ; /* -a == ~a + 1 (mod 2^n) for n-bit number
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_osk_bitops.h26 MALI_STATIC_INLINE void _mali_internal_clear_bit(u32 bit, u32 *addr) in _mali_internal_clear_bit() argument
28 MALI_DEBUG_ASSERT(bit < UINT32_BITS_MAX); in _mali_internal_clear_bit()
31 (*addr) &= ~(1 << bit); in _mali_internal_clear_bit()
34 MALI_STATIC_INLINE void _mali_internal_set_bit(u32 bit, u32 *addr)
36 MALI_DEBUG_ASSERT(bit < UINT32_BITS_MAX);
39 (*addr) |= (1 << bit);
42 MALI_STATIC_INLINE u32 _mali_internal_test_bit(u32 bit, u32 value)
44 MALI_DEBUG_ASSERT(bit < UINT32_BITS_MAX);
45 return value & (1 << bit);
61 negated = (u32)-inverted; /* -a == ~a + 1 (mod 2^n) for n-bit number
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/common/
H A Dmac_regdomain.c77 regclass->channel_bmap = bit(MAC_CHANNEL1) | in mac_init_regdomain_2g()
78 bit(MAC_CHANNEL2) | in mac_init_regdomain_2g()
79 bit(MAC_CHANNEL3) | in mac_init_regdomain_2g()
80 bit(MAC_CHANNEL4) | in mac_init_regdomain_2g()
81 bit(MAC_CHANNEL5) | in mac_init_regdomain_2g()
82 bit(MAC_CHANNEL6) | in mac_init_regdomain_2g()
83 bit(MAC_CHANNEL7) | in mac_init_regdomain_2g()
84 bit(MAC_CHANNEL8) | in mac_init_regdomain_2g()
85 bit(MAC_CHANNEL9) | in mac_init_regdomain_2g()
86 bit(MAC_CHANNEL1 in mac_init_regdomain_2g()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_atomic.h63 * The specified bit in the atomic setting variable is 1.
64 CNcomment:原子设置变量中指定bit位为1CNend
66 #define hi_atomic_bit_set_op(bit, v) (hi_atomic_bit_set(bit, v))
69 * The specified bit in the atomic setting variable is 0.
70 CNcomment:原子设置变量中指定bit位为0CNend
72 #define hi_atomic_bit_clear_op(bit, v) (hi_atomic_bit_clear(bit, v))
129 * The specified bit in the atomic setting variable is 1.CNcomment:原子设置变量中指定bit位为
143 hi_atomic_bit_set(hi_s32 bit, volatile hi_u32 *value) hi_atomic_bit_set() argument
168 hi_atomic_bit_clear(hi_s32 bit, volatile hi_u32 *value) hi_atomic_bit_clear() argument
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H A Dhi_wifi_api.h43 #ifndef bit
44 #define bit(x) (1U << (x)) macro
52 #define WIFI_CIPHER_TKIP bit(3)
59 #define WIFI_CIPHER_CCMP bit(4)
410 HI_WIFI_FRAME_TYPE_BEACON = bit(0),
411 HI_WIFI_FRAME_TYPE_PROBE_REQ = bit(1),
412 HI_WIFI_FRAME_TYPE_PROBE_RSP = bit(2),
1014 * 9. WEP supports 64 bit and 128 bit encryption.
1015 * for 64 bit encryptio
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/device/soc/rockchip/common/sdk_linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c74 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
374 .bit = PINCTRL_ROCKCHIP_ZERO,
376 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_ONE, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_TWO, .mask = 0x3},
377 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_TWO, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_FOUR, .mask = 0x3},
381 .bit = PINCTRL_ROCKCHIP_SIX,
386 .bit = PINCTRL_ROCKCHIP_EIGHT,
388 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_FIVE, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_TEN, .mask = 0x3},
392 .bit = PINCTRL_ROCKCHIP_TWELVE,
397 .bit = PINCTRL_ROCKCHIP_FOURTEEN,
402 .bit
769 rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask) rockchip_get_recalced_mux() argument
1383 u8 bit; rockchip_get_mux() local
1481 u8 bit; rockchip_set_mux() local
1577 px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) px30_calc_pull_reg_and_bit() argument
1606 px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) px30_calc_drv_reg_and_bit() argument
1635 px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) px30_calc_schmitt_reg_and_bit() argument
1664 rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1108_calc_pull_reg_and_bit() argument
1692 rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1108_calc_drv_reg_and_bit() argument
1721 rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1108_calc_schmitt_reg_and_bit() argument
1750 rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1126_calc_pull_reg_and_bit() argument
1785 rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1126_calc_drv_reg_and_bit() argument
1821 rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rv1126_calc_schmitt_reg_and_bit() argument
1855 rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3308_calc_schmitt_reg_and_bit() argument
1876 rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk1808_calc_pull_reg_and_bit() argument
1901 rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk1808_calc_drv_reg_and_bit() argument
1925 rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk1808_calc_slew_rate_reg_and_bit() argument
1949 rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk1808_calc_schmitt_reg_and_bit() argument
1972 rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk2928_calc_pull_reg_and_bit() argument
1987 rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3128_calc_pull_reg_and_bit() argument
2006 rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3188_calc_pull_reg_and_bit() argument
2038 rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3288_calc_pull_reg_and_bit() argument
2071 rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3288_calc_drv_reg_and_bit() argument
2100 rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3228_calc_pull_reg_and_bit() argument
2116 rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3228_calc_drv_reg_and_bit() argument
2132 rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3308_calc_pull_reg_and_bit() argument
2148 rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3308_calc_drv_reg_and_bit() argument
2165 rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3368_calc_pull_reg_and_bit() argument
2195 rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3368_calc_drv_reg_and_bit() argument
2226 rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3399_calc_pull_reg_and_bit() argument
2255 rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3399_calc_drv_reg_and_bit() argument
2282 rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3568_calc_slew_rate_reg_and_bit() argument
2307 rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3568_calc_pull_reg_and_bit() argument
2337 rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3568_calc_drv_reg_and_bit() argument
2388 u8 bit; rockchip_get_drive_perpin() local
2452 data >>= bit; rockchip_get_drive_perpin() local
2465 u8 bit; rockchip_set_drive_perpin() local
2599 u8 bit; rockchip_get_pull() local
2629 data >>= bit; rockchip_get_pull() local
2645 u8 bit; rockchip_set_pull() local
2720 rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3328_calc_schmitt_reg_and_bit() argument
2741 rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) rk3568_calc_schmitt_reg_and_bit() argument
2768 u8 bit; rockchip_get_schmitt() local
2781 data >>= bit; rockchip_get_schmitt() local
2798 u8 bit; rockchip_set_schmitt() local
2831 px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) px30_calc_slew_rate_reg_and_bit() argument
2859 u8 bit; rockchip_get_slew_rate() local
2872 data >>= bit; rockchip_get_slew_rate() local
2882 u8 bit; rockchip_set_slew_rate() local
[all...]
H A Dpinctrl-rockchip.h161 * @bit: index at register.
163 * @mask: mask bit
169 u8 bit; member
210 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit);
211 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit);
212 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit);
213 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit);
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_atomic.h70 * The specified bit in the atomic setting variable is 1.
71 CNcomment:原子设置变量中指定bit位为1CNend
73 #define hi_atomic_bit_set_op(bit, v) (hi_atomic_bit_set(bit, v))
76 * The specified bit in the atomic setting variable is 0.
77 CNcomment:原子设置变量中指定bit位为0CNend
79 #define hi_atomic_bit_clear_op(bit, v) (hi_atomic_bit_clear(bit, v))
146 * @brief The specified bit in the atomic setting variable is 1.CNcomment:原子设置变量中指定bit位为
163 hi_atomic_bit_set(hi_s32 bit, volatile hi_u32 *value) hi_atomic_bit_set() argument
192 hi_atomic_bit_clear(hi_s32 bit, volatile hi_u32 *value) hi_atomic_bit_clear() argument
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/device/soc/hisilicon/hi3751v350/sdk_linux/source/msp/drv/gpio/
H A Ddrv_gpio_intf.c41 hi_u32 bit; member
45 static hi_void gpio_proc_write_cmd_process(hi_u32 cmd, hi_u32 group, hi_u32 bit, hi_u32 bit_value) in gpio_proc_write_cmd_process() argument
53 ret = hi_drv_gpio_get_dir_bit(group * 8 + bit, &input); // 每组8个io口 in gpio_proc_write_cmd_process()
55 HI_PRINT("read dir error , group is %d , bit is %d\n", group, bit); in gpio_proc_write_cmd_process()
59 HI_PRINT("dir[%d][%d] = %s\n", group, bit, input ? "input" : "output"); in gpio_proc_write_cmd_process()
64 ret = hi_drv_gpio_set_dir_bit(group * 8 + bit, bit_value); // 每组8个io口 in gpio_proc_write_cmd_process()
66 HI_PRINT("write dir error, group is %d , bit is %d\n", group, bit); in gpio_proc_write_cmd_process()
70 HI_PRINT("dir[%d][%d] = %s\n", group, bit, bit_valu in gpio_proc_write_cmd_process()
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/compat/
H A Dhal_efuse.h27 #define hal_set_bit(src, bit) (src |= (1 << (bit)))
28 #define hal_clear_bit(src, bit) (src &= ~(1 << (bit)))
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_js_affinity.c191 /* A violation occurs when any bit in the left_set is also in the in kbase_js_affinity_is_violating()
228 u64 bit = 1ULL << bitnum; in kbase_js_affinity_retain_slot_cores() local
234 js_devdata->runpool_irq.slot_affinities[js] |= bit; in kbase_js_affinity_retain_slot_cores()
237 cores &= ~bit; in kbase_js_affinity_retain_slot_cores()
253 u64 bit = 1ULL << bitnum; in kbase_js_affinity_release_slot_cores() local
261 js_devdata->runpool_irq.slot_affinities[js] &= ~bit; in kbase_js_affinity_release_slot_cores()
264 cores &= ~bit; in kbase_js_affinity_release_slot_cores()
H A Dmali_kbase_pm_policy.c614 u64 bit = 1ULL << bitnum; in kbase_pm_request_cores() local
619 * of memory that is impossible on a 32-bit system and extremely in kbase_pm_request_cores()
620 * unlikely on a 64-bit system. */ in kbase_pm_request_cores()
624 kbdev->shader_needed_bitmap |= bit; in kbase_pm_request_cores()
628 cores &= ~bit; in kbase_pm_request_cores()
662 u64 bit = 1ULL << bitnum; in kbase_pm_unrequest_cores() local
670 kbdev->shader_needed_bitmap &= ~bit; in kbase_pm_unrequest_cores()
675 shader_cores &= ~bit; in kbase_pm_unrequest_cores()
739 u64 bit = 1ULL << bitnum; in kbase_pm_register_inuse_cores() local
747 kbdev->shader_needed_bitmap &= ~bit; in kbase_pm_register_inuse_cores()
792 u64 bit = 1ULL << bitnum; kbase_pm_release_cores() local
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_js_affinity.c206 /* A violation occurs when any bit in the left_set is also in the in kbase_js_affinity_is_violating()
247 u64 bit = 1ULL << bitnum; in kbase_js_affinity_retain_slot_cores() local
254 js_devdata->runpool_irq.slot_affinities[js] |= bit; in kbase_js_affinity_retain_slot_cores()
256 cores &= ~bit; in kbase_js_affinity_retain_slot_cores()
273 u64 bit = 1ULL << bitnum; in kbase_js_affinity_release_slot_cores() local
283 js_devdata->runpool_irq.slot_affinities[js] &= ~bit; in kbase_js_affinity_release_slot_cores()
285 cores &= ~bit; in kbase_js_affinity_release_slot_cores()
H A Dmali_kbase_pm_policy.c675 u64 bit = 1ULL << bitnum; in kbase_pm_request_cores() local
680 * of memory that is impossible on a 32-bit system and extremely in kbase_pm_request_cores()
681 * unlikely on a 64-bit system. */ in kbase_pm_request_cores()
685 kbdev->shader_needed_bitmap |= bit; in kbase_pm_request_cores()
689 cores &= ~bit; in kbase_pm_request_cores()
728 u64 bit = 1ULL << bitnum; in kbase_pm_unrequest_cores() local
736 kbdev->shader_needed_bitmap &= ~bit; in kbase_pm_unrequest_cores()
741 shader_cores &= ~bit; in kbase_pm_unrequest_cores()
807 u64 bit = 1ULL << bitnum; in kbase_pm_register_inuse_cores() local
815 kbdev->shader_needed_bitmap &= ~bit; in kbase_pm_register_inuse_cores()
860 u64 bit = 1ULL << bitnum; kbase_pm_release_cores() local
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dbcmnvram.h106 * @param bit bit value to get
109 extern char * nvram_get_bitflag(const char *name, const int bit);
155 * @param bit bit value to get
161 nvram_match_bitflag(const char *name, const int bit, const char *match) in nvram_match_bitflag() argument
163 const char *value = nvram_get_bitflag(name, bit); in nvram_match_bitflag()
208 * @param bit bit value to set
212 extern int nvram_set_bitflag(const char *name, const int bit, cons
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_hwcnt_types.h61 * An array of u64 bitfields, where each bit either enables exactly one
67 * A bitfield, where each bit corresponds to whether a block instance is
96 * Use 64-bit per counter in driver to avoid HW 32-bit register values
126 * @hdr_cnt: The number of 64-bit Block Headers in the block.
127 * @ctr_cnt: The number of 64-bit Block Counters in the block.
172 * @hdr_cnt: The number of 64-bit Block Headers in the block.
173 * @ctr_cnt: The number of 64-bit Block Counters in the block.
259 * array of u64 bitfields, each bit of which enables one hardware
261 * @clk_enable_map: An array of u64 bitfields, each bit o
512 const size_t bit = kbase_hwcnt_metadata_block_avail_bit() local
535 const size_t bit = kbase_hwcnt_metadata_block_avail_bit( kbase_hwcnt_metadata_block_instance_avail() local
812 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_value_enabled() local
830 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_enable_value() local
848 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_disable_value() local
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_hwcnt_types.h62 * An array of u64 bitfields, where each bit either enables exactly one
68 * A bitfield, where each bit corresponds to whether a block instance is
109 * @hdr_cnt: The number of 32-bit Block Headers in the block.
110 * @ctr_cnt: The number of 32-bit Block Counters in the block.
155 * @hdr_cnt: The number of 32-bit Block Headers in the block.
156 * @ctr_cnt: The number of 32-bit Block Counters in the block.
242 * array of u64 bitfields, each bit of which enables one hardware
244 * @clk_enable_map: An array of u64 bitfields, each bit of which enables cycle
406 * kbase_hwcnt_metadata_block_avail_bit() - Get the bit index into the avail
412 * Return: The bit inde
417 const size_t bit = kbase_hwcnt_metadata_block_avail_bit() local
436 const size_t bit = kbase_hwcnt_metadata_block_avail_bit(metadata, grp, blk) + blk_inst; kbase_hwcnt_metadata_block_instance_avail() local
673 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_value_enabled() local
689 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_enable_value() local
705 const size_t bit = val_idx % KBASE_HWCNT_BITFIELD_BITS; kbase_hwcnt_enable_map_block_disable_value() local
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/pinctrl/
H A Dpinctrl-rockchip.h309 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
310 * @recalced_mask: bit mask to indicate a need to recalulate the mask
350 * @bit: index at register.
352 * @mask: mask bit
358 u8 bit; member
407 int *reg, u8 *bit);
410 int *reg, u8 *bit);
413 int *reg, u8 *bit);
416 int *reg, u8 *bit);
/device/soc/rockchip/rk3588/kernel/include/linux/
H A Dpinctrl-rockchip.h309 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
310 * @recalced_mask: bit mask to indicate a need to recalulate the mask
350 * @bit: index at register.
352 * @mask: mask bit
358 u8 bit; member
407 int *reg, u8 *bit);
410 int *reg, u8 *bit);
413 int *reg, u8 *bit);
416 int *reg, u8 *bit);
/device/soc/rockchip/common/vendor/drivers/gpio/
H A Dgpio-rockchip.c97 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, u32 bit, u32 value, unsigned int offset) in rockchip_gpio_writel_bit() argument
104 data = BIT(bit % 0x10) | BIT(bit % 0x10 + 0x10); in rockchip_gpio_writel_bit()
106 data = BIT(bit % 0x10 + 0x10); in rockchip_gpio_writel_bit()
108 writel(data, bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_writel_bit()
111 data &= ~BIT(bit); in rockchip_gpio_writel_bit()
113 data |= BIT(bit); in rockchip_gpio_writel_bit()
119 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, u32 bit, unsigned int offset) in rockchip_gpio_readl_bit() argument
125 data = readl(bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_readl_bit()
126 data >>= bit in rockchip_gpio_readl_bit()
129 data >>= bit; rockchip_gpio_readl_bit() local
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/gpio/
H A Dgpio-rockchip.c97 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, u32 bit, u32 value, unsigned int offset) in rockchip_gpio_writel_bit() argument
104 data = BIT(bit % 0x10) | BIT(bit % 0x10 + 0x10); in rockchip_gpio_writel_bit()
106 data = BIT(bit % 0x10 + 0x10); in rockchip_gpio_writel_bit()
108 writel(data, bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_writel_bit()
111 data &= ~BIT(bit); in rockchip_gpio_writel_bit()
113 data |= BIT(bit); in rockchip_gpio_writel_bit()
119 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, u32 bit, unsigned int offset) in rockchip_gpio_readl_bit() argument
125 data = readl(bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_readl_bit()
126 data >>= bit in rockchip_gpio_readl_bit()
129 data >>= bit; rockchip_gpio_readl_bit() local
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/wal/
H A Dwal_cfg80211.c121 .types = bit(NL80211_IFTYPE_STATION),
126 .types = bit(NL80211_IFTYPE_AP),
130 .types = bit(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT),
135 .types = bit(NL80211_IFTYPE_MESH_POINT),
155 .rx = bit(IEEE80211_STYPE_ACTION >> 4)
159 .rx = bit(IEEE80211_STYPE_ACTION >> 4) |
160 bit(IEEE80211_STYPE_PROBE_REQ >> 4)
164 .rx = bit(IEEE80211_STYPE_ASSOC_REQ >> 4) |
165 bit(IEEE80211_STYPE_REASSOC_REQ >> 4) |
166 bit(IEEE80211_STYPE_PROBE_RE
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_net.h414 WIPHY_FLAG_CUSTOM_REGULATORY = bit(0),
415 WIPHY_FLAG_STRICT_REGULATORY = bit(1),
416 WIPHY_FLAG_DISABLE_BEACON_HINTS = bit(2),
417 WIPHY_FLAG_NETNS_OK = bit(3),
418 WIPHY_FLAG_PS_ON_BY_DEFAULT = bit(4),
419 WIPHY_FLAG_4ADDR_AP = bit(5),
420 WIPHY_FLAG_4ADDR_STATION = bit(6),
421 WIPHY_FLAG_CONTROL_PORT_PROTOCOL = bit(7),
422 WIPHY_FLAG_IBSS_RSN = bit(8),
423 WIPHY_FLAG_MESH_AUTH = bit(1
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S94 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
95 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
97 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
99 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache

Completed in 28 milliseconds

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