| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 25 #define SCLK_UART2 79 macro
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| H A D | rk3128-cru.h | 27 #define SCLK_UART2 79 macro
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| H A D | rk3188-cru-common.h | 22 #define SCLK_UART2 66 macro
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| H A D | rk1808-cru.h | 63 #define SCLK_UART2 62 macro
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| H A D | px30-cru.h | 27 #define SCLK_UART2 25 macro
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| H A D | rk3288-cru.h | 34 #define SCLK_UART2 79 macro
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| H A D | rk3368-cru.h | 32 #define SCLK_UART2 79 macro
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| H A D | rk3568-cru.h | 354 #define SCLK_UART2 291 macro
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| H A D | rk3399-cru.h | 41 #define SCLK_UART2 83 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 63 #define SCLK_UART2 62 macro
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| H A D | rv1126-cru.h | 87 #define SCLK_UART2 20 macro
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| H A D | rk3568-cru.h | 354 #define SCLK_UART2 291 macro
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| H A D | rk3588-cru.h | 190 #define SCLK_UART2 187 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 159 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3128.c | 182 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3368.c | 358 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
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| H A D | clk-rk3188.c | 252 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3328.c | 208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
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| H A D | clk-rv1108.c | 164 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 193 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 294 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, RK3308_CLKGATE_CON(2), 4, GFLAGS),
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| H A D | clk-rk3288.c | 214 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
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| H A D | clk-px30.c | 487 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, PX30_CLKGATE_CON(11), 3,
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 608 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0, RK1808_CLKGATE_CON(11), 15, GFLAGS),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 899 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, RK3568_CLKGATE_CON(28), 3, GFLAGS),
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