| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3128-cru.h | 20 #define SCLK_SPI0 65 macro
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| H A D | rk3188-cru-common.h | 25 #define SCLK_SPI0 69 macro
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| H A D | rk1808-cru.h | 74 #define SCLK_SPI0 73 macro
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| H A D | px30-cru.h | 38 #define SCLK_SPI0 36 macro
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| H A D | rk3288-cru.h | 20 #define SCLK_SPI0 65 macro
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| H A D | rk3368-cru.h | 21 #define SCLK_SPI0 65 macro
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| H A D | rk3399-cru.h | 29 #define SCLK_SPI0 71 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 74 #define SCLK_SPI0 73 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 326 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0, RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3368.c | 448 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3188.c | 337 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, RK2928_CLKGATE_CON(2),
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| H A D | clk-rk3228.c | 370 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3308.c | 324 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3288.c | 379 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-px30.c | 526 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3399.c | 1046 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 661 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
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