| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 19 #define SCLK_SDMMC 68 macro
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| H A D | rk3128-cru.h | 22 #define SCLK_SDMMC 68 macro
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| H A D | rk3188-cru-common.h | 28 #define SCLK_SDMMC 72 macro
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| H A D | rk1808-cru.h | 48 #define SCLK_SDMMC 47 macro
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| H A D | px30-cru.h | 61 #define SCLK_SDMMC 59 macro
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| H A D | rk3288-cru.h | 23 #define SCLK_SDMMC 68 macro
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| H A D | rk3368-cru.h | 24 #define SCLK_SDMMC 68 macro
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| H A D | rk3399-cru.h | 34 #define SCLK_SDMMC 76 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 48 #define SCLK_SDMMC 47 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 251 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
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| H A D | clk-rk3128.c | 268 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
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| H A D | clk-rk3368.c | 455 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3188.c | 342 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0, RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
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| H A D | clk-rk3328.c | 452 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0, RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
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| H A D | clk-rv1108.c | 498 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
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| H A D | clk-rk3228.c | 310 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
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| H A D | clk-rk3308.c | 383 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| H A D | clk-rk3288.c | 386 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
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| H A D | clk-px30.c | 385 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| H A D | clk-rk3399.c | 695 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, RK3399_CLKSEL_CON(16), 8, 3,
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 491 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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