| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 21 #define SCLK_EMMC 71 macro
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| H A D | rk3128-cru.h | 24 #define SCLK_EMMC 71 macro
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| H A D | rk3188-cru-common.h | 30 #define SCLK_EMMC 74 macro
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| H A D | rk1808-cru.h | 43 #define SCLK_EMMC 42 macro
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| H A D | px30-cru.h | 59 #define SCLK_EMMC 57 macro
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| H A D | rk3288-cru.h | 26 #define SCLK_EMMC 71 macro
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| H A D | rk3368-cru.h | 26 #define SCLK_EMMC 71 macro
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| H A D | rk3399-cru.h | 36 #define SCLK_EMMC 78 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 43 #define SCLK_EMMC 42 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 257 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3128.c | 274 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
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| H A D | clk-rk3368.c | 459 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
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| H A D | clk-rk3188.c | 346 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0, RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, RK2928_CLKGATE_CON(2),
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| H A D | clk-rk3328.c | 458 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0, RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
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| H A D | clk-rv1108.c | 507 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
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| H A D | clk-rk3228.c | 319 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
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| H A D | clk-rk3308.c | 401 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| H A D | clk-rk3288.c | 392 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
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| H A D | clk-px30.c | 364 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| H A D | clk-rk3399.c | 719 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0,
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 481 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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