Searched refs:RESET_COMPLETED (Results 1 - 15 of 15) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/backend/ |
| H A D | mali_kbase_gpu_regmap_csf.h | 260 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ macro
280 #define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED | POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ)
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| H A D | mali_kbase_gpu_regmap_jm.h | 280 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ macro
298 (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED)
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/backend/ |
| H A D | mali_kbase_device_hw_jm.c | 62 if (val & RESET_COMPLETED) { in kbase_gpu_interrupt()
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/backend/ |
| H A D | mali_kbase_gpu_regmap_jm.h | 277 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ macro
294 #define GPU_IRQ_REG_COMMON (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \
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| H A D | mali_kbase_gpu_regmap_csf.h | 342 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ macro
362 #define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED \
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/ |
| H A D | mali_kbase_device_hw_jm.c | 63 if (val & RESET_COMPLETED) in kbase_gpu_interrupt()
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| H A D | mali_kbase_device_hw_csf.c | 133 if (val & RESET_COMPLETED) in kbase_gpu_interrupt()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 43 #define RESET_COMPLETED \ macro
55 (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED)
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 47 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. Intended to use with SOFT_RESET macro
56 #define GPU_IRQ_REG_ALL (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_device_hw.c | 234 if (val & RESET_COMPLETED) in kbase_gpu_interrupt()
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| H A D | mali_kbase_pm_driver.c | 142 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
1190 * Wait for the %RESET_COMPLETED IRQ to occur, then reset the waiting state.
1407 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED, in kbase_pm_do_reset()
1421 /* Wait for the RESET_COMPLETED interrupt to be raised */ in kbase_pm_do_reset()
1434 RESET_COMPLETED) { in kbase_pm_do_reset()
1457 /* Wait for the RESET_COMPLETED interrupt to be raised */ in kbase_pm_do_reset()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_device_hw.c | 221 if (val & RESET_COMPLETED) { in kbase_gpu_interrupt()
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| H A D | mali_kbase_pm_driver.c | 135 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
1082 * Wait for the %RESET_COMPLETED IRQ to occur, then reset the waiting state.
1274 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED, NULL); in kbase_pm_do_reset()
1286 /* Wait for the RESET_COMPLETED interrupt to be raised */ in kbase_pm_do_reset()
1298 if (kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL) & RESET_COMPLETED) { in kbase_pm_do_reset()
1319 /* Wait for the RESET_COMPLETED interrupt to be raised */ in kbase_pm_do_reset()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_driver.c | 267 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
2533 * Wait for the %RESET_COMPLETED IRQ to occur, then reset the waiting state.
2797 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED);
2810 /* Wait for the RESET_COMPLETED interrupt to be raised */
2824 RESET_COMPLETED)) {
2858 /* Wait for the RESET_COMPLETED interrupt to be raised */
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_driver.c | 236 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
1904 * Wait for the %RESET_COMPLETED IRQ to occur, then reset the waiting state.
2150 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED);
2162 /* Wait for the RESET_COMPLETED interrupt to be raised */
2174 if ((kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)) & RESET_COMPLETED)) {
2201 /* Wait for the RESET_COMPLETED interrupt to be raised */
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