Home
last modified time | relevance | path

Searched refs:MMU_REG (Results 1 - 25 of 30) sorted by relevance

12

/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_mmu_hw_direct.c141 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
143 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
223 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
225 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
342 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask, kctx); in kbase_mmu_hw_clear_fault()
366 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), kctx) | MMU_PAGE_FAULT(as->number); in kbase_mmu_hw_enable_fault()
372 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask, kctx); in kbase_mmu_hw_enable_fault()
H A Dmali_kbase_irq_linux.c91 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_handler()
261 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_test_handler()
274 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
306 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
307 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c34 /* MMU_REG(r) */
77 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
H A Dmali_kbase_pm_driver.c915 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
916 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
935 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
936 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_disable_interrupts_nolock()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_mmu_hw_direct.c145 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
147 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
245 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
247 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask, kctx); in kbase_mmu_hw_clear_fault()
396 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), kctx) | in kbase_mmu_hw_enable_fault()
403 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask, kctx); in kbase_mmu_hw_enable_fault()
H A Dmali_kbase_irq_linux.c94 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_handler()
269 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_test_handler()
281 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
315 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
316 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c58 /*MMU_REG(r)*/
115 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
H A Dmali_kbase_pm_driver.c1022 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1023 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1044 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
1045 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_disable_interrupts_nolock()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_jm.c323 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
325 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
407 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
409 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
H A Dmali_kbase_mmu_csf.c366 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
368 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
430 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
432 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_jm.c289 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
291 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
371 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_hw_direct.c320 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
344 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)) | in kbase_mmu_hw_enable_fault()
352 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask); in kbase_mmu_hw_enable_fault()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_hw_direct.c226 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
250 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)) | MMU_PAGE_FAULT(as->number); in kbase_mmu_hw_enable_fault()
257 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask); in kbase_mmu_hw_enable_fault()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_irq_linux.c103 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_handler()
301 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_test_handler()
314 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
346 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
347 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c41 /* MMU_REG(r) */
84 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_irq_linux.c102 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_handler()
302 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_test_handler()
314 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
348 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
349 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c62 /*MMU_REG(r)*/
121 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
H A Dmali_kbase_model_linux.c99 MMU_REG(MMU_IRQ_STATUS)))) { in serve_mmu_irq()
H A Dmali_kbase_model_dummy.c1252 else if (addr == MMU_REG(MMU_IRQ_MASK)) {
1254 } else if (addr == MMU_REG(MMU_IRQ_CLEAR)) {
1780 } else if (addr == MMU_REG(MMU_IRQ_MASK)) {
1782 } else if (addr == MMU_REG(MMU_IRQ_RAWSTAT)) {
1784 } else if (addr == MMU_REG(MMU_IRQ_STATUS)) {
H A Dmali_kbase_pm_driver.c2243 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
2246 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFF);
2248 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF);
2268 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0);
2269 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h177 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
203 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h253 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
277 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h256 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
280 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c245 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
250 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK))); in kbase_csf_debug_dump_registers()
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h197 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
223 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))

Completed in 24 milliseconds

12