| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 141 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
143 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
223 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
225 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
366 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), kctx) | MMU_PAGE_FAULT(as->number); in kbase_mmu_hw_enable_fault()
372 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask, kctx); in kbase_mmu_hw_enable_fault()
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| H A D | mali_kbase_debug_job_fault_backend.c | 35 static int mmu_reg_snapshot[] = {MMU_IRQ_MASK, MMU_IRQ_STATUS};
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| H A D | mali_kbase_irq_linux.c | 307 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
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| H A D | mali_kbase_pm_driver.c | 916 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
935 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 145 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
147 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
245 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
247 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
396 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), kctx) | in kbase_mmu_hw_enable_fault()
403 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask, kctx); in kbase_mmu_hw_enable_fault()
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| H A D | mali_kbase_debug_job_fault_backend.c | 60 MMU_IRQ_MASK,
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| H A D | mali_kbase_irq_linux.c | 316 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
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| H A D | mali_kbase_pm_driver.c | 1023 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1044 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/backend/ |
| H A D | mali_kbase_mmu_jm.c | 323 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
325 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
407 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
409 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
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| H A D | mali_kbase_mmu_csf.c | 366 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
368 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
430 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
432 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/backend/ |
| H A D | mali_kbase_mmu_jm.c | 289 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
291 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
371 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 344 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)) | in kbase_mmu_hw_enable_fault()
352 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask); in kbase_mmu_hw_enable_fault()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 250 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)) | MMU_PAGE_FAULT(as->number); in kbase_mmu_hw_enable_fault()
257 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask); in kbase_mmu_hw_enable_fault()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 42 static int mmu_reg_snapshot[] = {MMU_IRQ_MASK, MMU_IRQ_STATUS};
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| H A D | mali_kbase_irq_linux.c | 347 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
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| H A D | mali_kbase_pm_driver.c | 1697 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFF);
1699 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF);
1719 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0);
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 64 MMU_IRQ_MASK,
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| H A D | mali_kbase_irq_linux.c | 349 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
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| H A D | mali_kbase_pm_driver.c | 2246 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFF);
2248 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF);
2268 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0);
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| H A D | mali_kbase_model_dummy.c | 1252 else if (addr == MMU_REG(MMU_IRQ_MASK)) {
1780 } else if (addr == MMU_REG(MMU_IRQ_MASK)) {
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 181 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ macro
237 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 257 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ macro
304 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 260 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ macro
308 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_reset_gpu.c | 247 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_csf_debug_dump_registers()
250 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK))); in kbase_csf_debug_dump_registers()
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 201 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ macro
252 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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