| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 24 #define MHZ (1000000) macro
125 ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type); in rockchip_ddrclk_scpi_set_rate()
140 return (MHZ * ddr_clk_cached); in rockchip_ddrclk_scpi_recalc_rate()
142 return (MHZ * scpi_ddr_get_clk_rate()); in rockchip_ddrclk_scpi_recalc_rate()
148 rate = rate / MHZ; in rockchip_ddrclk_scpi_round_rate()
151 return (rate * MHZ); in rockchip_ddrclk_scpi_round_rate()
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| H A D | clk-pll.c | 68 #define MHZ (1000UL * 1000UL) macro
73 #define PLL_FREF_MAX (2200 * MHZ)
75 #define PLL_FVCO_MIN (440 * MHZ)
76 #define PLL_FVCO_MAX (2200 * MHZ)
79 #define PLL_FOUT_MAX (2200 * MHZ)
86 #define MIN_FOUTVCO_FREQ (800 * MHZ)
87 #define MAX_FOUTVCO_FREQ (2000 * MHZ)
215 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MH in rockchip_pll_clk_set_by_auto()
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/wtdg/ |
| H A D | hi_wtdg.c | 97 #ifndef MHZ
98 #define MHZ (1000 * 1000) macro
101 static const unsigned long g_rate = 3 * MHZ; /* 3MHZ */
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| /device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/ |
| H A D | mpp_rkvdec2.c | 662 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 0x12c * MHZ);
in rkvdec2_init()
663 mpp_set_clk_info_rate_hz(&dec->core_clk_info, CLK_MODE_DEFAULT, 0xc8 * MHZ);
in rkvdec2_init()
664 mpp_set_clk_info_rate_hz(&dec->cabac_clk_info, CLK_MODE_DEFAULT, 0xc8 * MHZ);
in rkvdec2_init()
665 mpp_set_clk_info_rate_hz(&dec->hevc_cabac_clk_info, CLK_MODE_DEFAULT, 0x12c * MHZ);
in rkvdec2_init()
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| H A D | mpp_rkvdec.c | 1165 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, CLK_MODE_THR * MHZ);
in rkvdec_init()
1166 mpp_set_clk_info_rate_hz(&dec->core_clk_info, CLK_MODE_DEFAULT, CLK_MODE_TW * MHZ);
in rkvdec_init()
1167 mpp_set_clk_info_rate_hz(&dec->cabac_clk_info, CLK_MODE_DEFAULT, CLK_MODE_TW * MHZ);
in rkvdec_init()
1168 mpp_set_clk_info_rate_hz(&dec->hevc_cabac_clk_info, CLK_MODE_DEFAULT, CLK_MODE_THR * MHZ);
in rkvdec_init()
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| H A D | mpp_common.h | 29 #define MHZ (1000 * 1000) macro
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| H A D | mpp_rkvenc.c | 1135 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in rkvenc_init()
1136 mpp_set_clk_info_rate_hz(&enc->core_clk_info, CLK_MODE_DEFAULT, 0x258 * MHZ);
in rkvenc_init()
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| H A D | mpp_jpgdec.c | 399 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in jpgdec_init()
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| H A D | mpp_vepu1.c | 574 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in vepu_init()
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| H A D | mpp_vdpu2.c | 475 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in vdpu_init()
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| H A D | mpp_vdpu1.c | 523 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in vdpu_init()
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| H A D | mpp_rkvenc2.c | 1184 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 0X12c * MHZ);
in rkvenc_init()
1185 mpp_set_clk_info_rate_hz(&enc->core_clk_info, CLK_MODE_DEFAULT, 0x258 * MHZ);
in rkvenc_init()
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| H A D | mpp_iep2.c | 760 mpp_set_clk_info_rate_hz(&iep->aclk_info, CLK_MODE_DEFAULT, 0x12c * MHZ);
in iep2_init()
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| H A D | mpp_vepu2.c | 688 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 0x12C * MHZ);
in vepu_init()
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| /device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/ |
| H A D | mpp_rkvdec2.c | 670 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvdec2_init()
671 mpp_set_clk_info_rate_hz(&dec->core_clk_info, CLK_MODE_DEFAULT, 200 * MHZ); in rkvdec2_init()
672 mpp_set_clk_info_rate_hz(&dec->cabac_clk_info, CLK_MODE_DEFAULT, 200 * MHZ); in rkvdec2_init()
673 mpp_set_clk_info_rate_hz(&dec->hevc_cabac_clk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvdec2_init()
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| H A D | mpp_rkvdec.c | 1224 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvdec_init()
1225 mpp_set_clk_info_rate_hz(&dec->core_clk_info, CLK_MODE_DEFAULT, 200 * MHZ); in rkvdec_init()
1226 mpp_set_clk_info_rate_hz(&dec->cabac_clk_info, CLK_MODE_DEFAULT, 200 * MHZ); in rkvdec_init()
1227 mpp_set_clk_info_rate_hz(&dec->hevc_cabac_clk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvdec_init()
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| H A D | mpp_common.h | 27 #define MHZ (1000 * 1000) macro
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| H A D | mpp_rkvenc.c | 1186 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvenc_init()
1187 mpp_set_clk_info_rate_hz(&enc->core_clk_info, CLK_MODE_DEFAULT, 600 * MHZ); in rkvenc_init()
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| H A D | mpp_vdpu1.c | 540 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in vdpu_init()
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| H A D | mpp_vepu1.c | 600 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in vepu_init()
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| H A D | mpp_vdpu2.c | 493 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in vdpu_init()
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| H A D | mpp_jpgdec.c | 411 mpp_set_clk_info_rate_hz(&dec->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in jpgdec_init()
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| H A D | mpp_rkvenc2.c | 1177 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in rkvenc_init()
1178 mpp_set_clk_info_rate_hz(&enc->core_clk_info, CLK_MODE_DEFAULT, 600 * MHZ); in rkvenc_init()
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| H A D | mpp_vepu2.c | 710 mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in vepu_init()
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| H A D | mpp_iep2.c | 810 mpp_set_clk_info_rate_hz(&iep->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ); in iep2_init()
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