Searched refs:GRF_VI_CON0 (Results 1 - 6 of 6) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 28 #define GRF_VI_CON0 (0x0340)
macro
324 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
325 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
326 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
327 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
328 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
329 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
330 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
331 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 28 #define GRF_VI_CON0 (0x0340) macro
329 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
330 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
331 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
332 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
333 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
334 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
335 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
336 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
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| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/ |
| H A D | regs.h | 46 #define GRF_VI_CON0 0x430
macro
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| H A D | rkisp.c | 1493 regmap_update_bits(dev->hw_dev->grf, GRF_VI_CON0, ISP_CIF_DATA_WIDTH_MASK, data_width);
in rkisp_config_dvp()
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| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/ |
| H A D | regs.h | 49 #define GRF_VI_CON0 0x430 macro
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| H A D | rkisp.c | 1531 regmap_update_bits(dev->hw_dev->grf, GRF_VI_CON0, in rkisp_config_dvp()
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