Searched refs:DCLK_VOP0 (Results 1 - 9 of 9) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3288-cru.h | 87 #define DCLK_VOP0 190 macro
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| H A D | rk3568-cru.h | 286 #define DCLK_VOP0 223 macro
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| H A D | rk3399-cru.h | 139 #define DCLK_VOP0 180 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk3568-cru.h | 286 #define DCLK_VOP0 223 macro
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| H A D | rk3588-cru.h | 624 #define DCLK_VOP0 628 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3288.c | 328 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8,
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| H A D | clk-rk3399.c | 273 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 791 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 2073 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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Completed in 24 milliseconds