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Searched refs:CYCLE_COUNT_HI (Results 1 - 8 of 8) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
35 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
37 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_time.c36 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
38 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_time.c159 GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_cycle_cnt()
163 GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_cycle_cnt()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h70 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ macro
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h81 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ macro
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h83 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ macro
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h81 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ macro

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