| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/ |
| H A D | mali_kbase_device_hw.c | 52 CLEAN_CACHES_COMPLETED)) { in busy_wait_cache_clean_irq()
59 "CLEAN_CACHES_COMPLETED bit stuck, might be caused by slow/unstable GPU clock or possible faulty FPGA connector\n"); in busy_wait_cache_clean_irq()
65 /* Clear the interrupt CLEAN_CACHES_COMPLETED bit. */ in busy_wait_cache_clean_irq()
67 CLEAN_CACHES_COMPLETED); in busy_wait_cache_clean_irq()
84 /* 1. Check if CLEAN_CACHES_COMPLETED irq mask bit is set. in kbase_gpu_cache_flush_and_busy_wait()
86 * CLEAN_CACHES_COMPLETED irq to be raised. in kbase_gpu_cache_flush_and_busy_wait()
93 if (irq_mask & CLEAN_CACHES_COMPLETED) { in kbase_gpu_cache_flush_and_busy_wait()
96 irq_mask & ~CLEAN_CACHES_COMPLETED); in kbase_gpu_cache_flush_and_busy_wait()
110 /* Clear the interrupt CLEAN_CACHES_COMPLETED bit. */ in kbase_gpu_cache_flush_and_busy_wait()
112 CLEAN_CACHES_COMPLETED); in kbase_gpu_cache_flush_and_busy_wait()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/backend/ |
| H A D | mali_kbase_device_hw_jm.c | 82 if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
88 } else if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/ |
| H A D | mali_kbase_device_hw_jm.c | 81 if (val & CLEAN_CACHES_COMPLETED) in kbase_gpu_interrupt()
86 } else if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
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| H A D | mali_kbase_device_hw_csf.c | 162 if (val & CLEAN_CACHES_COMPLETED) in kbase_gpu_interrupt()
167 } else if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/ |
| H A D | mali_kbase_device_hw.c | 99 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED); in kbase_gpu_start_cache_clean_nolock()
140 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~CLEAN_CACHES_COMPLETED); in kbase_clean_caches_done()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/backend/ |
| H A D | mali_kbase_gpu_regmap_csf.h | 263 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
276 * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
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| H A D | mali_kbase_gpu_regmap_jm.h | 284 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
295 * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_instr_backend.c | 51 irq_mask | CLEAN_CACHES_COMPLETED, NULL); in kbasep_instr_hwcnt_cacheclean()
400 irq_mask & ~CLEAN_CACHES_COMPLETED, NULL); in kbase_clean_caches_done()
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| H A D | mali_kbase_device_hw.c | 240 if (val & CLEAN_CACHES_COMPLETED) in kbase_gpu_interrupt()
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| H A D | mali_kbase_jm_rb.c | 1832 CLEAN_CACHES_COMPLETED) == 0) in kbase_gpu_cacheclean()
1835 /* clear the CLEAN_CACHES_COMPLETED irq */ in kbase_gpu_cacheclean()
1837 CLEAN_CACHES_COMPLETED); in kbase_gpu_cacheclean()
1839 CLEAN_CACHES_COMPLETED, NULL); in kbase_gpu_cacheclean()
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| H A D | mali_kbase_pm_driver.c | 142 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_instr_backend.c | 45 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED, NULL); in kbasep_instr_hwcnt_cacheclean()
364 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~CLEAN_CACHES_COMPLETED, NULL); in kbase_clean_caches_done()
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| H A D | mali_kbase_device_hw.c | 229 if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
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| H A D | mali_kbase_jm_rb.c | 1599 (kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL) & CLEAN_CACHES_COMPLETED) == 0) { in kbase_gpu_cacheclean()
1603 /* clear the CLEAN_CACHES_COMPLETED irq */ in kbase_gpu_cacheclean()
1604 KBASE_TRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, NULL, 0u, CLEAN_CACHES_COMPLETED); in kbase_gpu_cacheclean()
1605 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), CLEAN_CACHES_COMPLETED, NULL); in kbase_gpu_cacheclean()
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| H A D | mali_kbase_pm_driver.c | 135 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/backend/ |
| H A D | mali_kbase_gpu_regmap_jm.h | 281 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
292 * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
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| H A D | mali_kbase_gpu_regmap_csf.h | 345 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
358 * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 52 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 54 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ macro
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_driver.c | 267 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_driver.c | 236 const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED; in mali_cci_flush_l2()
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