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/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeRISCV_64.c38 SLJIT_ASSERT((imm & 0x800) != 0); in load_immediate()
43 if ((imm & 0x800) != 0) in load_immediate()
59 if (imm & 0x800) in load_immediate()
63 SLJIT_ASSERT((high & 0x800) != 0); in load_immediate()
67 if ((high & 0x800) != 0) in load_immediate()
94 if ((high & 0x800) != 0) in load_immediate()
105 SLJIT_ASSERT((imm & 0x800) != 0); in load_immediate()
110 if ((imm & 0x800) != 0) in load_immediate()
133 if ((init_value & 0x800) != 0) in emit_const()
141 if ((high & 0x800) ! in emit_const()
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H A DsljitNativeRISCV_32.c35 if (imm & 0x800) in load_immediate()
48 if ((init_value & 0x800) != 0) in emit_const()
60 if ((new_target & 0x800) != 0) in sljit_set_jump_addr()
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
H A Dpasemi_nand.c37 while (len > 0x800) { in pasemi_read_buf()
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
39 buf += 0x800; in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
48 while (len > 0x800) { in pasemi_write_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
50 buf += 0x800; in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
H A Dcs553x_nand.c57 #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
125 while (unlikely(len > 0x800)) { in cs553x_data_in()
126 memcpy_fromio(buf, cs553x->mmio, 0x800); in cs553x_data_in()
127 buf += 0x800; in cs553x_data_in()
128 len -= 0x800; in cs553x_data_in()
137 while (unlikely(len > 0x800)) { in cs553x_data_out()
138 memcpy_toio(cs553x->mmio, buf, 0x800); in cs553x_data_out()
139 buf += 0x800; in cs553x_data_out()
140 len -= 0x800; in cs553x_data_out()
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/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
H A Dpasemi_nand.c39 while (len > 0x800) { in pasemi_read_buf()
40 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
41 buf += 0x800; in pasemi_read_buf()
42 len -= 0x800; in pasemi_read_buf()
50 while (len > 0x800) { in pasemi_write_buf()
51 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
52 buf += 0x800; in pasemi_write_buf()
53 len -= 0x800; in pasemi_write_buf()
H A Dcs553x_nand.c56 #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
119 while (unlikely(len > 0x800)) { in cs553x_data_in()
120 memcpy_fromio(buf, cs553x->mmio, 0x800); in cs553x_data_in()
121 buf += 0x800; in cs553x_data_in()
122 len -= 0x800; in cs553x_data_in()
131 while (unlikely(len > 0x800)) { in cs553x_data_out()
132 memcpy_toio(cs553x->mmio, buf, 0x800); in cs553x_data_out()
133 buf += 0x800; in cs553x_data_out()
134 len -= 0x800; in cs553x_data_out()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
85 nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000); in gf119_disp_super()
165 const u32 hoff = head->id * 0x800; in gf119_disp_intr()
200 const u32 hoff = head->id * 0x800; in gf119_disp_init()
211 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); in gf119_disp_init()
212 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp); in gf119_disp_init()
217 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in gf119_disp_init()
218 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp); in gf119_disp_init()
247 const u32 hoff = head->id * 0x800; in gf119_disp_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dga100.c180 return !(nvkm_rd32(device, 0x04015c + (runq->id * 0x800)) & 0x0000e000); in ga100_runq_idle()
187 u32 inte = nvkm_rd32(device, 0x040180 + (runq->id * 0x800)); in ga100_runq_intr_1()
188 u32 intr = nvkm_rd32(device, 0x040148 + (runq->id * 0x800)); in ga100_runq_intr_1()
208 nvkm_mask(device, 0x0400ac + (runq->id * 0x800), 0x00030000, 0x00030000); in ga100_runq_intr_1()
214 nvkm_wr32(device, 0x0401a0 + (runq->id * 0x800), stat); in ga100_runq_intr_1()
217 nvkm_wr32(device, 0x040148 + (runq->id * 0x800), intr); in ga100_runq_intr_1()
225 u32 inte = nvkm_rd32(device, 0x040170 + (runq->id * 0x800)); in ga100_runq_intr_0()
226 u32 intr = nvkm_rd32(device, 0x040108 + (runq->id * 0x800)); in ga100_runq_intr_0()
252 nvkm_wr32(device, 0x040190 + (runq->id * 0x800), stat); in ga100_runq_intr_0()
255 nvkm_wr32(device, 0x040108 + (runq->id * 0x800), int in ga100_runq_intr_0()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h792 #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100)
794 #define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104)
795 #define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108)
796 #define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200)
799 #define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280)
802 #define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300)
807 #define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800)
813 #define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800)
817 #define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800)
821 #define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800)
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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h792 #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100)
794 #define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104)
795 #define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108)
796 #define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200)
799 #define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280)
802 #define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300)
807 #define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800)
813 #define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800)
817 #define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800)
821 #define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800)
[all...]
/kernel/linux/linux-5.10/arch/riscv/kernel/
H A Dmodule.c51 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
65 u32 imm11 = (offset & 0x800) << (20 - 11); in apply_r_riscv_jal_rela()
91 u16 imm11 = (offset & 0x800) << (12 - 11); in apply_r_riscv_rvc_jump_rela()
118 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_pcrel_hi20_rela()
160 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_hi20_rela()
169 s32 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_lo12_i_rela()
179 s32 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_lo12_s_rela()
204 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_got_hi20_rela()
228 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_call_plt_rela()
248 hi20 = (offset + 0x800) in apply_r_riscv_call_rela()
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/kernel/linux/linux-6.6/arch/riscv/kernel/
H A Dmodule.c52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
66 u32 imm11 = (offset & 0x800) << (20 - 11); in apply_r_riscv_jal_rela()
92 u16 imm11 = (offset & 0x800) << (12 - 11); in apply_r_riscv_rvc_jump_rela()
119 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_pcrel_hi20_rela()
161 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_hi20_rela()
170 s32 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_lo12_i_rela()
180 s32 hi20 = ((s32)v + 0x800) & 0xfffff000; in apply_r_riscv_lo12_s_rela()
205 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_got_hi20_rela()
229 hi20 = (offset + 0x800) & 0xfffff000; in apply_r_riscv_call_plt_rela()
249 hi20 = (offset + 0x800) in apply_r_riscv_call_rela()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgk20a.c43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_ibus_init_ibus_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_ibus_init_ibus_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_ibus_init_ibus_ring()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk20a.c43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_privring_init_privring_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_privring_init_privring_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_privring_init_privring_ring()
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
14 #define DMTE0_IRQ evt2irq(0x800)
24 #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
36 #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
14 #define DMTE0_IRQ evt2irq(0x800)
24 #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
36 #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
/kernel/linux/linux-5.10/drivers/net/arcnet/
H A Darc-rimi.c243 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_reset()
249 arcnet_writeb(TESTvalue, ioaddr, -0x800); /* fake reset */ in arcrimi_reset()
266 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_setmask()
274 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_status()
282 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_command()
291 void __iomem *memaddr = lp->mem_start + 0x800 + bufnum * 512 + offset; in arcrimi_copy_to_card()
300 void __iomem *memaddr = lp->mem_start + 0x800 + bufnum * 512 + offset; in arcrimi_copy_from_card()
/kernel/linux/linux-6.6/drivers/net/arcnet/
H A Darc-rimi.c244 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_reset()
250 arcnet_writeb(TESTvalue, ioaddr, -0x800); /* fake reset */ in arcrimi_reset()
267 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_setmask()
275 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_status()
283 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_command()
292 void __iomem *memaddr = lp->mem_start + 0x800 + bufnum * 512 + offset; in arcrimi_copy_to_card()
301 void __iomem *memaddr = lp->mem_start + 0x800 + bufnum * 512 + offset; in arcrimi_copy_from_card()
/third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/
H A DBMPSet.java81 list4kStarts[0] = findCodePoint(0x800, 0, listLength - 1); in BMPSet()
325 * Set bits in a bit rectangle in "vertical" bit organization. start<limit<=0x800
366 // limit<=0x800. If limit==0x800 then limitLead=32 and limitTrail=0. in set32x64Bits()
398 while (start < 0x800) { in initBits()
399 set32x64Bits(table7FF, start, limit <= 0x800 ? limit : 0x800); in initBits()
400 if (limit > 0x800) { in initBits()
401 start = 0x800; in initBits()
414 int minStart = 0x800; in initBits()
[all...]
/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/impl/
H A DBMPSet.java83 list4kStarts[0] = findCodePoint(0x800, 0, listLength - 1); in BMPSet()
327 * Set bits in a bit rectangle in "vertical" bit organization. start<limit<=0x800
368 // limit<=0x800. If limit==0x800 then limitLead=32 and limitTrail=0. in set32x64Bits()
400 while (start < 0x800) { in initBits()
401 set32x64Bits(table7FF, start, limit <= 0x800 ? limit : 0x800); in initBits()
402 if (limit > 0x800) { in initBits()
403 start = 0x800; in initBits()
416 int minStart = 0x800; in initBits()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h119 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
137 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
149 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
391 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
535 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
605 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
723 #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
851 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
957 #define FEATURE_STATUS__LHTC_ON_MASK 0x800
3907 #define THM_TMON2_CTRL__INT_MEAS_EN_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h119 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
137 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
149 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
391 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
535 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
605 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
723 #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
851 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
957 #define FEATURE_STATUS__LHTC_ON_MASK 0x800
3907 #define THM_TMON2_CTRL__INT_MEAS_EN_MASK 0x800
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h14 # define ADVERTISE_PAUSE_ASYM 0x800
25 #define GBCR_MANUAL_AS_MASTER 0x800
30 #define GBSR_LP_1000FULL 0x800
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h14 # define ADVERTISE_PAUSE_ASYM 0x800
25 #define GBCR_MANUAL_AS_MASTER 0x800
30 #define GBSR_LP_1000FULL 0x800
/kernel/linux/linux-6.6/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
74 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
81 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
91 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
93 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
94 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
95 #define LYNX_28G_LNaRECR2(lane) (0x800
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