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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h101 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200
133 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200
323 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
567 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
591 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
787 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
1309 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
1375 #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
1487 #define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200
1615 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h101 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200
133 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200
323 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
567 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
591 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
787 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
1309 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
1375 #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
1487 #define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200
1615 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
[all...]
/kernel/linux/linux-5.10/drivers/firewire/
H A Dohci.h105 #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
106 #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
/kernel/linux/linux-5.10/arch/m68k/include/asm/
H A Dm5307sim.h121 #define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
125 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
/kernel/linux/linux-5.10/arch/sh/boards/mach-se/770x/
H A Dsetup.c132 .end = SH_TSU_BASE + 0x200 - 1,
160 .end = SH_TSU_BASE + 0x200 - 1,
/kernel/linux/linux-5.10/arch/s390/include/asm/
H A Dpci_dma.h79 #define ZPCI_TABLE_PROTECTED 0x200
83 #define ZPCI_TABLE_PROT_MASK 0x200
/kernel/linux/linux-6.6/arch/m68k/include/asm/
H A Dm5307sim.h121 #define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
125 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
/kernel/linux/linux-6.6/arch/s390/include/asm/
H A Dpci_dma.h79 #define ZPCI_TABLE_PROTECTED 0x200
83 #define ZPCI_TABLE_PROT_MASK 0x200
/kernel/linux/linux-6.6/arch/sh/boards/mach-se/770x/
H A Dsetup.c132 .end = SH_TSU_BASE + 0x200 - 1,
160 .end = SH_TSU_BASE + 0x200 - 1,
/kernel/linux/linux-5.10/drivers/isdn/hardware/mISDN/
H A Dhfc_pci.h166 #define B_SUB_VAL 0x200
199 u_char fill1[0x200];
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgm107.c45 const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); in gm107_ltc_cbc_wait()
76 u32 base = 0x140400 + (c * 0x2000) + (s * 0x200); in gm107_ltc_intr_lts()
/kernel/linux/linux-5.10/sound/soc/qcom/qdsp6/
H A Dq6afe.h76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
/kernel/linux/linux-6.6/drivers/firewire/
H A Dohci.h105 #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
106 #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgm107.c45 const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); in gm107_ltc_cbc_wait()
76 u32 base = 0x140400 + (c * 0x2000) + (s * 0x200); in gm107_ltc_intr_lts()
/kernel/linux/linux-6.6/drivers/isdn/hardware/mISDN/
H A Dhfc_pci.h166 #define B_SUB_VAL 0x200
199 u_char fill1[0x200];
/kernel/linux/linux-6.6/sound/soc/qcom/qdsp6/
H A Dq6afe.h76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
/third_party/mesa3d/src/gallium/drivers/nouveau/
H A Dnouveau_vp3_video.h38 #define SLICE_SIZE 0x200
39 #define VP_OFFSET 0x200
/third_party/musl/include/
H A Dfcntl.h65 #define AT_REMOVEDIR 0x200
67 #define AT_EACCESS 0x200
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h83 /* 2. Page2(0x200) */
472 #define bGlobalResetB 0x200
548 #define bIGFromCCK 0x200
578 #define bRFSI_ANTSWB 0x200
613 #define bAD7PowerUp 0x200
652 #define bCCKRxAGCFormat 0x200
769 #define bTRSSIFreq 0x200
919 #define bCFOAntSumD 0x200
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h229 #define bGlobalResetB 0x200
300 #define bIGFromCCK 0x200
327 #define bRFSI_ANTSWB 0x200
359 #define bAD7PowerUp 0x200
395 #define bCCKRxAGCFormat 0x200
518 #define bTRSSIFreq 0x200
675 #define bCFOAntSumD 0x200
/kernel/linux/linux-5.10/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h76 * 2. Page2(0x200)
387 #define bGlobalResetB 0x200
460 #define bIGFromCCK 0x200
485 #define bRFSI_ANTSWB 0x200
516 #define bAD7PowerUp 0x200
556 #define bCCKRxAGCFormat 0x200
672 #define bTRSSIFreq 0x200
821 #define bCFOAntSumD 0x200
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_global_conf_masks.h45 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200
251 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
333 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200
665 #define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200
811 #define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200
839 #define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200
1357 #define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h187 #define bGlobalResetB 0x200
258 #define bIGFromCCK 0x200
284 #define bRFSI_ANTSWB 0x200
315 #define bAD7PowerUp 0x200
351 #define bCCKRxAGCFormat 0x200
474 #define bTRSSIFreq 0x200
631 #define bCFOAntSumD 0x200
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h83 /* 2. Page2(0x200) */
468 #define bGlobalResetB 0x200
544 #define bIGFromCCK 0x200
573 #define bRFSI_ANTSWB 0x200
607 #define bAD7PowerUp 0x200
646 #define bCCKRxAGCFormat 0x200
763 #define bTRSSIFreq 0x200
913 #define bCFOAntSumD 0x200
/kernel/linux/linux-6.6/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h75 * 2. Page2(0x200)
386 #define bGlobalResetB 0x200
459 #define bIGFromCCK 0x200
484 #define bRFSI_ANTSWB 0x200
515 #define bAD7PowerUp 0x200
555 #define bCCKRxAGCFormat 0x200
671 #define bTRSSIFreq 0x200
820 #define bCFOAntSumD 0x200

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