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/kernel/linux/linux-5.10/drivers/soc/renesas/
H A Dr8a7795-sysc.c30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
36 { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
/kernel/linux/linux-6.6/drivers/pmdomain/renesas/
H A Dr8a7795-sysc.c30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
36 { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
/kernel/linux/linux-5.10/drivers/memory/tegra/
H A Dtegra30.c994 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
995 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
996 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
997 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
998 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
999 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1000 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1001 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1002 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1003 TEGRA30_MC_RESET(MPCORE, 0x200,
[all...]
/kernel/linux/linux-6.6/drivers/memory/tegra/
H A Dtegra30.c1199 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
1200 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
1201 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
1202 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
1203 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
1204 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1205 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1206 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1207 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1208 TEGRA30_MC_RESET(MPCORE, 0x200,
[all...]
H A Dtegra114.c1086 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
1087 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
1088 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
1089 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
1090 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
1091 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
1092 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
1093 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
1094 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
1095 TEGRA114_MC_RESET(MPCORELP, 0x200,
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/sn/sn0/
H A Dkldir.h138 #define IP27_LAUNCH_STRIDE 0x200
179 #define IP27_NMI_KREGS_CPU_SIZE 0x200
184 #define IP27_NMI_EFRAME_SIZE 0x200
/kernel/linux/linux-6.6/arch/mips/include/asm/sn/sn0/
H A Dkldir.h138 #define IP27_LAUNCH_STRIDE 0x200
179 #define IP27_NMI_KREGS_CPU_SIZE 0x200
184 #define IP27_NMI_EFRAME_SIZE 0x200
/kernel/linux/linux-5.10/drivers/nvmem/
H A Dsunxi_sid.c77 * On Allwinner H3, the value on the 0x200 offset of the SID controller seems
177 .size = 0x200,
181 .value_offset = 0x200,
187 .value_offset = 0x200,
193 .value_offset = 0x200,
194 .size = 0x200,
/test/xts/acts/location/geolocation_standard/entry/src/ohosTest/js/test/
H A DLocationTest.test.js25 let LocationRequestPriority = {UNSET : 0x200 ,ACCURACY : 0x201 ,LOW_POWER : 0x202 ,FIRST_FIX :0x203}
204 let currentLocationRequest = { "priority": 0x200, "scenario": 0x301, "timeoutMs": 1000, "maxAccuracy": 0 };
257 let currentLocationRequest = { "priority": 0x200, "scenario": 0x302, "timeoutMs": 1000, "maxAccuracy": 10 };
282 let currentLocationRequest = { "priority": 0x200, "scenario": 0x303, "timeoutMs": 1000, "maxAccuracy": 10 };
306 let currentLocationRequest = { "priority": 0x200, "scenario": 0x304, "timeoutMs": 1000, "maxAccuracy": 0 };
331 let currentLocationRequest1 = { "priority": 0x200, "scenario": 0x305, "timeoutMs": 1000, "maxAccuracy": 10 };
332 let currentLocationRequest2 = { "priority": 0x200, "scenario": 0x301, "timeoutMs": 1000, "maxAccuracy": 10 };
638 let requestInfo = {"priority":0x200, "scenario":0x301, "timeInterval":5,
669 let requestInfo = {"priority":0x200, "scenario":0x302, "timeInterval":1,
700 let requestInfo = {"priority":0x200, "scenari
[all...]
/kernel/linux/linux-5.10/drivers/media/platform/qcom/camss/
H A Dcamss-ispif.c47 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
49 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
54 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
59 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
62 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
65 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
68 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
70 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
71 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/
H A Dcamss-ispif.c48 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
50 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
55 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
60 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
63 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
66 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
69 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
71 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
72 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (
[all...]
/kernel/linux/linux-5.10/arch/x86/kvm/
H A Dmtrr.c30 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: in msr_mtrr_valid()
76 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); in kvm_mtrr_valid()
332 index = (msr - 0x200) / 2; in update_mtrr()
350 index = (msr - 0x200) / 2; in set_var_mtrr_msr()
351 is_mtrr_mask = msr - 0x200 - 2 * index; in set_var_mtrr_msr()
426 index = (msr - 0x200) / 2; in kvm_mtrr_get_msr()
427 is_mtrr_mask = msr - 0x200 - 2 * index; in kvm_mtrr_get_msr()
/kernel/linux/linux-6.6/drivers/nvmem/
H A Dsunxi_sid.c89 * On Allwinner H3, the value on the 0x200 offset of the SID controller seems
188 .size = 0x200,
192 .value_offset = 0x200,
198 .value_offset = 0x200,
203 .value_offset = 0x200,
204 .size = 0x200,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h113 #define HW_DEBUG__HW_09_DEBUG_MASK 0x200
243 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
279 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
303 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
335 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
417 #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
441 #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
463 #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
541 #define BACO_CNTL__PWRGOOD_BF_MASK 0x200
647 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h113 #define HW_DEBUG__HW_09_DEBUG_MASK 0x200
243 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
279 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
303 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
335 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
417 #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
441 #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
463 #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
541 #define BACO_CNTL__PWRGOOD_BF_MASK 0x200
647 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
[all...]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
H A Dtsi108.h30 #define TSI108_UART0_SIZE 0x200
31 #define TSI108_GPIO_SIZE 0x200
32 #define TSI108_UART1_SIZE 0x200
/kernel/linux/linux-5.10/arch/arc/include/asm/
H A Dcache.h103 #define DC_CTRL_RGN_OP_INV 0x200
104 #define DC_CTRL_RGN_OP_MSK 0x200
122 #define SLC_CTRL_RGN_OP_INV 0x200
/kernel/linux/linux-6.6/arch/arc/include/asm/
H A Dcache.h99 #define DC_CTRL_RGN_OP_INV 0x200
100 #define DC_CTRL_RGN_OP_MSK 0x200
118 #define SLC_CTRL_RGN_OP_INV 0x200
/kernel/linux/linux-6.6/arch/powerpc/include/asm/
H A Dtsi108.h30 #define TSI108_UART0_SIZE 0x200
31 #define TSI108_GPIO_SIZE 0x200
32 #define TSI108_UART1_SIZE 0x200
/kernel/linux/linux-6.6/include/uapi/linux/
H A Dnetlink.h71 #define NLM_F_MATCH 0x200 /* return all matching */
77 #define NLM_F_EXCL 0x200 /* Do not touch, if it exists */
83 #define NLM_F_BULK 0x200 /* Delete multiple objects */
87 #define NLM_F_ACK_TLVS 0x200 /* extended ACK TVLs were included */
/third_party/ffmpeg/libavcodec/tests/
H A Dcabac.c49 } else if (c->dec.low < 0x200) { in renorm_cabac_encoder()
54 c->dec.low -= 0x200; in renorm_cabac_encoder()
89 if (c->dec.low < 0x200) { in put_cabac_bypass()
93 c->dec.low -= 0x200; in put_cabac_bypass()
/third_party/lzma/C/
H A D7zCrcOpt.c23 ^ (table + 0x200)[((v >> 8) & 0xFF)] in CrcUpdateT4()
50 ^ (table + 0x200)[((d >> 8) & 0xFF)] in CrcUpdateT8()
81 ^ (table + 0x200)[((v >> 16) & 0xFF)] in CrcUpdateT1_BeT4()
109 ^ (table + 0x200)[((d >> 16) & 0xFF)] in CrcUpdateT1_BeT8()
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dpsoc_global_conf_masks.h132 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
288 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK 0x200
314 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK 0x200
340 #define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK 0x200
366 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK 0x200
392 #define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK 0x200
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpsoc_global_conf_masks.h132 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
288 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK 0x200
314 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK 0x200
340 #define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK 0x200
366 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK 0x200
392 #define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK 0x200
/kernel/linux/linux-5.10/tools/testing/selftests/kvm/include/s390x/
H A Dprocessor.h10 #define REGION_ENTRY_PROTECT 0x200 /* region protection bit */
19 #define PAGE_PROTECT 0x200 /* HW read-only bit */

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