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/kernel/linux/linux-5.10/drivers/video/fbdev/via/
H A Dhw.c201 /* Index 0x14~0x17 */
202 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
334 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
335 0x14,
338 {0x1C, 0x14,
[all...]
/kernel/linux/linux-6.6/drivers/video/fbdev/via/
H A Dhw.c201 /* Index 0x14~0x17 */
202 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
334 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
335 0x14,
338 {0x1C, 0x14,
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h136 #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
172 #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
1166 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
1222 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
1304 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1310 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
1320 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1392 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1402 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1424 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h136 #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
172 #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
1166 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
1222 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
1304 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1310 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
1320 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1392 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1402 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1424 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h237 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14
270 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
326 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
387 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x14
431 #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14
460 #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14
531 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
564 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
597 #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x14
692 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h237 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14
270 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
326 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
387 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x14
431 #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14
460 #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14
531 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
564 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
597 #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x14
708 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/hid/
H A Dhid-kye.c38 0x14, /* Logical Minimum (0), */
57 0x14, /* Logical Minimum (0), */
76 0x14, /* Logical Minimum (0), */
95 0x14, /* Logical Minimum (0), */
110 0x14, /* Logical Minimum (0), */
138 0x14, /* Logical Minimum (0), */
157 0x14, /* Logical Minimum (0), */
182 0x14, /* Logical Minimum (0), */
202 0x14, /* Logical Minimum (0), */
234 0x14, /* Logica
[all...]
/third_party/backends/backend/
H A Dgt68xx_devices.c255 {0x14, 0x07, 0x14, 0x07, 0x14, 0x07}, /* Default offset/gain */
499 {0x14, 0x07, 0x14, 0x07, 0x14, 0x07}, /* Default offset/gain */
992 {0x14, 0x05, 0x12, 0x05, 0x17, 0x0c}, /* Default offset/gain */
1043 {0x14, 0x07, 0x14, 0x07, 0x14,
[all...]
/third_party/icu/icu4c/source/common/
H A Dpropname_data.h33 0xb,0xc,0xd,0xe,0xf,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,
115 0x18,3,0x62,0xc3,0x14,0x68,0x32,0x6f,0x42,0x73,0x13,0x70,0x61,0x63,0x65,0x5f,
117 0x61,0x6b,0xc3,0x14,0x73,0xa2,0x49,0x74,0xa4,0x3b,0x75,3,0x63,0xd9,0x40,0xc,
135 0x67,0x13,0x72,0x65,0x61,0x6b,0xc3,0x13,0x14,0x69,0x74,0x69,0x76,0x65,0x65,1,
144 0x14,0x64,0x69,0x63,0x61,0x6c,0x55,0x1e,0x67,0x69,0x6f,0x6e,0x61,0x6c,0x69,0x6e,
152 0x65,0x72,0x63,0x6f,0x64,0x65,0x70,0x6f,0x69,0x6e,0x74,0x51,0x14,0x6d,0x65,0x72,
167 0x77,0x18,0x68,0x69,0x74,0x65,0x73,0x70,0x61,0x63,0x65,0x77,0x14,0x79,0x6e,0x74,
192 0x79,0x70,0x65,0xc3,0xb,0x10,0x78,0x3a,0x14,0x64,0x69,0x67,0x69,0x74,0x3b,0x10,
198 0x65,0x61,0x6b,0xc3,0x12,0x14,0x78,0x74,0x65,0x6e,0x64,0x37,0x12,0x61,0x73,0x65,
214 0x61,0x20,0x14,
[all...]
/third_party/skia/third_party/externals/icu/source/common/
H A Dpropname_data.h34 9,0xa,0xb,0xc,0xd,0xe,0xf,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,
115 0x18,3,0x62,0xc3,0x14,0x68,0x32,0x6f,0x42,0x73,0x13,0x70,0x61,0x63,0x65,0x5f,
117 0x61,0x6b,0xc3,0x14,0x73,0xa2,0x49,0x74,0xa4,0x3b,0x75,3,0x63,0xd9,0x40,0xc,
135 0x67,0x13,0x72,0x65,0x61,0x6b,0xc3,0x13,0x14,0x69,0x74,0x69,0x76,0x65,0x65,1,
143 0xf1,0x71,0xa4,0x43,0x72,2,0x61,0x28,0x65,0x32,0x69,0x9d,0x14,0x64,0x69,0x63,
147 0x74,0x65,0x72,0x63,0x6f,0x64,0x65,0x70,0x6f,0x69,0x6e,0x74,0x51,0x14,0x6d,0x65,
162 0x38,0x77,0x18,0x68,0x69,0x74,0x65,0x73,0x70,0x61,0x63,0x65,0x77,0x14,0x79,0x6e,
187 0x74,0x79,0x70,0x65,0xc3,0xb,0x10,0x78,0x3a,0x14,0x64,0x69,0x67,0x69,0x74,0x3b,
193 0x72,0x65,0x61,0x6b,0xc3,0x12,0x14,0x78,0x74,0x65,0x6e,0x64,0x37,0x12,0x61,0x73,
208 0x20,0x14,
[all...]
/kernel/linux/linux-5.10/drivers/clk/axis/
H A Dclk-artpec6.c182 clkdata->syscon_base + 0x14, i, 1, in artpec6_clkctrl_probe()
186 muxreg = readl(clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
188 writel(muxreg, clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
195 muxreg = readl(clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
197 writel(muxreg, clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imxrt1050.c117 hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1, in imxrt1050_clocks_probe()
129 hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1, in imxrt1050_clocks_probe()
131 hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1, in imxrt1050_clocks_probe()
134 hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3); in imxrt1050_clocks_probe()
135 hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2); in imxrt1050_clocks_probe()
/kernel/linux/linux-6.6/drivers/clk/axis/
H A Dclk-artpec6.c182 clkdata->syscon_base + 0x14, i, 1, in artpec6_clkctrl_probe()
186 muxreg = readl(clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
188 writel(muxreg, clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
195 muxreg = readl(clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
197 writel(muxreg, clkdata->syscon_base + 0x14); in artpec6_clkctrl_probe()
/third_party/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-const-ands-a32.h38 0xff, 0x97, 0x14, 0xd2 // ands le r9 r4 0x03fc0000
50 0xab, 0xe2, 0x14, 0x52 // ands pl r14 r4 0xb000000a
110 0xab, 0xf0, 0x14, 0x82 // ands hi r15 r4 0x000000ab
134 0xab, 0x92, 0x14, 0x62 // ands vs r9 r4 0xb000000a
146 0xab, 0x2c, 0x14, 0x22 // ands cs r2 r4 0x0000ab00
179 0xff, 0x89, 0x14, 0x62 // ands vs r8 r4 0x003fc000
290 0xab, 0xe3, 0x14, 0x72 // ands vc r14 r4 0xac000002
302 0xab, 0x44, 0x14, 0xd2 // ands le r4 r4 0xab000000
305 0xff, 0xb6, 0x14, 0xc2 // ands gt r11 r4 0x0ff00000
338 0xab, 0x92, 0x14,
[all...]
H A Dassembler-cond-rd-rn-operand-const-ands-t32.h137 0x14, 0xf4, 0xab, 0x09 // ands al r9 r4 0x00558000
203 0x14, 0xf0, 0xff, 0x03 // ands al r3 r4 0x000000ff
227 0x14, 0xf4, 0xff, 0x5e // ands al r14 r4 0x00001fe0
281 0x14, 0xf4, 0x2b, 0x77 // ands al r7 r4 0x000002ac
305 0x14, 0xf4, 0xff, 0x75 // ands al r5 r4 0x000001fe
314 0x14, 0xf4, 0x2b, 0x59 // ands al r9 r4 0x00002ac0
347 0x14, 0xf0, 0x2b, 0x61 // ands al r1 r4 0x0ab00000
374 0x14, 0xf0, 0x7f, 0x52 // ands al r2 r4 0x3fc00000
398 0x14, 0xf0, 0xab, 0x62 // ands al r2 r4 0x05580000
437 0x14,
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h89 #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
229 #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
336 #define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
435 #define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
477 #define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
722 #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
1883 #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
2075 #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
2542 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
2615 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h89 #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
229 #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
336 #define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
435 #define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
477 #define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
722 #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
1883 #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
2075 #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
2542 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
2615 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/arch/arm64/kernel/
H A Drelocate_kernel.S36 mov x14, xzr /* x14 = entry ptr */
72 mov x14, x12
83 ldr x16, [x14], #8
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
H A Damplc_dio200.c202 .sdinfo = { 0x00, 0x08, 0x0c, 0x10, 0x14, 0x3f },
218 .sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f },
227 .sdinfo = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x3f },
/kernel/linux/linux-6.6/drivers/comedi/drivers/
H A Damplc_dio200.c202 .sdinfo = { 0x00, 0x08, 0x0c, 0x10, 0x14, 0x3f },
218 .sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f },
227 .sdinfo = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x3f },
/third_party/typescript/tests/baselines/reference/
H A DdeclarationEmitDestructuringArrayPattern4.js3 var [x14, ...a6] = [1, 2, 3];
14 var _a = [1, 2, 3], x14 = _a[0], a6 = _a.slice(1);
25 declare var x14: number, a6: [number, number];
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h66 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
84 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
102 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
204 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
246 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
344 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
366 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
460 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
562 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
622 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
[all...]
H A Duvd_3_1_sh_mask.h66 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
84 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
102 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
204 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
246 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
340 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
362 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
456 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
558 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
616 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h66 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
84 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
102 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
204 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
246 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
340 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
362 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
456 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
558 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
616 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
[all...]
H A Duvd_4_2_sh_mask.h66 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
84 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
102 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
204 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
246 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
344 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
366 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
460 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
562 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
622 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
[all...]

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